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Claims  |
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What is claimed is:
1. A microprocessor system, comprising:
a. a first large scale integration device on a first semiconductor chip
forming a central processing unit which comprises:
1. an internal data bus;
2. at least one input/output port coupled to said internal data bus for
entering data into and for receiving data from said system;
3. first storage means disposed for storing instruction codes to be
executed by said system, said first storage means having input terminals
coupled to said internal data bus and having output terminals;
4. first decoding means having input terminals coupled to said output
terminals of said first storage means, said first decoding means having
first and second output terminals for supplying first and second control
signals, respectively, for the microprocessor system in accordance with
said instruction codes;
5. An arithmetic logic unit having two operand input terminals thereto and
result output terminals therefrom, wherein a first of said operand input
terminals is coupled to said internal data bus;
6. second storage means having input terminals coupled to said result
output terminals of said arithmetic logic unit and output terminals
coupled to the second of said operand input terminals of said arithmetic
logic unit;
7. a random access memory having data input terminals coupled to said
result output terminals of said arithmetic logic unit, output terminals
coupled to said first operand input terminals of said arithmetic logic
unit, and address input terminals coupled to said output terminals of said
first storage means;
8. means for transmitting said instruction codes from said first storage
means to one or more of said, first decoding means, said arithmetic logic
unit, and said random access memory;
9. gating means coupling said result output terminals of said arithmetic
logic unit to said internal data bus; and,
10. means coupling said first output terminals of said first decoding means
to said input/output port, said first and second storage means, said
arithmetic logic unit, said random access memory, said means for
transmitting, and said gating means, whereby operation of said central
processing unit is controlled by said first control signals in accordance
with said instruction codes;
b. a second large scale integration device on a second semiconductor chip
forming a memory circuit which comprises:
1. a third storage means for storing a multiplicity of the instruction
codes for said system, said third storage means having output terminals
coupled to said internal data bus in said first semiconductor chip,
2. second decoding means having input terminals coupled to said second
output terminals of said first decoding means on said first semiconductor
chip, said second decoding means being disposed for generating third
control signals at output terminals of said second decoding means in
accordance with said second signals; and,
3. first addressing means having input terminals coupled to said output
terminals of said second decoding means and output terminals coupled to
address input terminals of said third storage means, whereby said
instruction codes are retrieved from said third storage means in response
to said second control signals from said first decoding means in said
central processing unit on said first semiconductor chip; and,
c. means for interrupting system operations comprising an interrupt logic
means disposed on said first semiconductor chip, an interrupt control
means and an interrupt address generation means disposed on said second
semiconductor chip, said interrupt logic means having a first input
terminal disposed for receiving an interrupt request signal from said
interrupt control means, a first output terminal coupled to an interrupt
control means, a first output terminal coupled to an interrupt terminal of
said first decoding means, a second input disposed for receiving a status
portion of said first control signals from said first decoding means, and
a second output disposed for supplying an interrupt interrogate signal to
said interrupt control means;
said interrupt control means having a first input terminal coupled to said
second output terminal of said interrupt logic means for receiving said
interrupt interrogate signal, a first output terminal coupled to said
first input terminal of said interrupt logic means, a second input
terminal disposed for receiving an external interrupt signal, and a second
output terminal coupled to said interrupt address generation means; and
said interrupt address generation means having output terminals coupled to
said address input terminals of said third storage means, wherein
execution of operation by said microprocessor system in accordance with a
first sequence of said instruction codes is interrupted in response to an
interrupt signal to change to a second sequence of instruction codes
retrieved from said third storage means at an address generated by said
interrupt address generation means.
2. The microprocessor system of claim 1 further characterized by said
second large scale integration device including at least one input/output
port coupled to said data output terminals of said third storage means.
3. The microprocessor system of claim 1 further characterized by said
system including an additional plurality of large scale integration
devices on separate semiconductor chips each forming a memory circuit
which comprises:
a. a fourth storage means for storing a multiplicity of the instruction
codes for said system, said fourth storage means having output terminals
coupled to said internal data bus in said first semiconductor chip;
b. third decoding means having input terminals coupled to said second
output terminals of said first decoding means on said first semiconductor
chip, said third decoding means being disposed for generating fourth
control signals at output terminals of said third decoding means in
accordance with said second signals; and
c. second addressing means having input terminals coupled to said output
terminals of said third decoding means and output terminals coupled to
address input terminals of said third storage means, thereby to retrieve
selected instruction codes from said fourth storage means in response to
said second control signals from said first decoding means in said central
processing unit on said first semiconductor chip.
4. The microprocessor system of claim 1 further characterized by said
central processing unit including a clock circuit having a control input
terminal coupled to said first output terminals of said first decoding
means, said clock circuit disposed for providing a system clocking signal
of a first frequency in response to a first state of said first control
signals and a second frequency in response to a second state of said first
control signals.
5. The microprocessor system as in claim 4 further characterized by said
second large scale integration device including clock circuit means having
an input terminal disposed for receiving said system clocking signal and
output terminals disposed for supplying clock signals to said second large
scale integration device.
6. The microprocessor system as in claim 5 further characterized by said
second large scale integration device including a timer means having input
terminals coupled to said output terminals of said third storage means,
control input terminals coupled to said output terminals of said clock
circuit means, and an output terminal coupled to a third input terminal of
said interrupt control means, said timer means being disposed for
providing a time delay for interrupt operations in response to data
supplied thereto from said third storage means.
7. The microprocessor system as in claim 1 further characterized by said
first large scale integration device including a fourth storage means
having input terminals coupled to said result output terminals of said
arithmetic logic unit, output terminals coupled to said second operand
input terminals of said arithmetic logic unit, and a control input
terminal coupled to said first output terminals of said first decoding
means, said fourth storage means being disposed for storing information as
to the status of said arithmetic logic unit.
8. The miroprocessor system as in claim 1 further characterized by said
first large scale integration device including a second addressing means
having input terminals coupled to said result output terminals of said
arithmetic logic unit, first output terminals coupled to said address
input terminals of said random access memory, and second output terminals
coupled to said first operand input terminals of said arithmetic logic
unit.
9. The microprocessor system as in claim 1 further characterized by said
first addressing means on said second large scale integration device
including a program counter having input terminals, and output terminals
coupled to said address input terminals of said third storage means.
10. The microprocessor system as in claim 9 further characterized by said
first addressing means on said second large scale integration device
including a fifth storage means having input terminals coupled to said
output terminals of said program counter and output terminals coupled to
said adress input terminals of said third storage means, said fifth
storagemeans being disposed for storing an instruction code address.
11. The microprocessor system as in claim 1 further characterized by said
second large scale integration device including at least two input/output
ports coupled to said data output terminals of said third storage means.
12. The microprocessor system as in claim 11 further characterized by said
second large scale integration device including an input/output port
address select means having input terminals coupled to said output
terminals of said third storage means, a first output terminal coupled to
a control input terminal of a first of said at least two input/output
ports, and a second output terminal coupled to a control input terminal of
a second of said at least two input/output ports, said input/output port
address select means being disposed for selecting one of said at least two
input/output ports in accordance with data supplied from said third
storage means. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
Field of the Invention
This invention relates to a microprocessor system and, more particularly,
to a microprocessor system having a central processing unit that employs
an external memory containing a program counter.
Prior Art
The development of large-scale integrated circuits (LSI) has made possible
the design of microprocessor systems which are capable of performing
specialized computer functions. A microprocessor may comprise the control
and processing portion of a small computer. Microprocessors, like all
computer processors, can perform both arithmetic and logic functions in a
bit-parallel manner under the direction of a stored program.
Microprocessors, then, are inherently programmable. When placed in a
system with peripheral memory circuits to provide the control program, and
with input-and-output circuits, a microprocessor system is obtained which
has a power of computation less than that of a minicomputer. As large
scale integration technology advances, however, the power of computation
of microprocessor systems approaches that of minicomputers.
Microprocessor systems generally derive their organization from the
organizational and architectural concepts established from computers and
minicomputers. The placement of a central processing unit, memory
circuits, input-and-output circuits and miscellaneous support circuitry on
a minimum number of integrated circuit chips inherently entails the
employment of a small number of packages, which have a large number of
external connectors or pins.
The typical prior art microprocessor architecture requires that a program
counter be included in the central processing unit, and that this counter
select the particular external memory to be addressed for retrieving
program instruction codes. The use of a program counter in the CPU
requires the use of a multiple-bus structure between the CPU and the
memory. That is, at least one separate dedicated bus is employed for
transferring data, and another dedicated bus for transferring addresses to
the memory. The net result is that a larger number of pins are required on
the CPU chip. Another approach in the prior art has been to employ a
single bus between the CPU and an external memory, wherein data and
addresses are time-multiplexed along the bus. This technique has a
distinct disadvantage of requiring more complex circuitry, and a loss of
process time for the multiplexing operation.
SUMMARY OF THE INVENTION
In accordance with the present invention, a microprocessor system is
provided which has at least two separate large scale integration devices
comprising a central processing unit large scale integration device
including an arithmetic logic unit and at least one input/output port. The
central processing unit requires an external program counter containing
memory addresses of instruction codes to be used by the central processing
unit. A first memory large scale integration device is provided which is
electrically coupled to said central processing unit and includes a memory
and the program counter. The program counter cooperates with the first
central processing unit large scale integration device to select the
instruction codes for operating the microprocessor in a manner determined
by the instruction codes.
The microprocessor system of the present invention incorporates a
single-chip central processing unit of large scale integration which
contains the standard elements of a central processing unit including
input-and-output ports, a program logic array, an arithmetic logic unit,
and a scratch pad memory; but which does not contain a program counter. At
least one separate memory large scale integration device on a single chip
is also provided which contains its own dedicated program counter. The
dedicated program counter is driven in synchronism with the operation of
the central processing unit so that appropriate control signals are
transmitted from the central processing unit to control the program
counter. If more than one separate memory large scale integration device
is incorporated in the microprocessor system, each additional memory
device includes its own dedicated program counter which operates in
synchronism with the central processing unit. In these multiple-memory
systems, the dedicated program counters operate in response to control
signals from the central processing unit so that each memory will provide
instruction codes at the appropriate time to the central processing unit.
An advantage of the system of the present invention is that a minimum
number of separate components are required to construct a microprocessor
system. That is, a basic microprocessor system is implemented with only
two semiconductor chips.
Another advantage of the present invention is that the circuitry required
for input-and-output device coupling is minimized. That is, separate
clocking circuits for input-and-output devices has been eliminated.
Still another advantage of the present invention is that the system
architecture takes advantage of restrictions imposed on large scale
integration of semiconductor devices.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the microprocessor system of the present
invention;
FIG. 1a is a schematic diagram of an alternate type of external circuit for
controlling the frequency of the CPU internal oscillator;
FIG. 2 is a block diagram of the single-chip large scale integration
central processing unit (CPU) of the microprocessor system of the present
invention;
FIG. 2a is a logic diagram of the clocking circuits 56;
FIG. 2b is a timing diagram illustrating the timing relationship of the
clock signals generated in the clock circuits 56;
FIG. 3 is a block diagram of the sequential control circuit for the CPU;
FIG. 4 is a logic diagram of the one bit position of a typical
input-and-output port;
FIG. 5 is a logic diagram of one bit position of the transfer gate and
instruction register within the CPU;
FIG. 6 is a logic diagram of the interrupt logic within the CPU;
FIG. 7 is a unitary diagram showing the relationship between FIGS. 7a and
7b;
FIGS. 7a and 7b are a combination logic and block diagram of the
accumulator register, the status register and the arithmetic logic unit of
the CPU;
FIG. 8 is a logic diagram of the BCD carry and BCD correction circuit for
the arithmetic logic unit;
FIG. 9 is a logic diagram of the carry/overflow circuit for the arithmetic
logic unit;
FIG. 10 is a logic diagram for the indirect RAM address register and the
address gating for the RAM within the CPU;
FIG. 11 is a block diagram of the single-chip large scale integration ROM
circuit of the present invention;
FIG. 12 is a logic diagram of the I/O port address select circuit;
FIG. 13 is a logic diagram of the interrupt control circuit;
FIG. 14 is a logic diagram of the clock circuits for the ROM circuit;
FIG. 15 is a logic diagram of the timer and the interrupt address
generator;
FIG. 16 is a combined logic-block diagram of the program counter, stack
register and data counter for the ROM circuit;
FIG. 17 is a unitary diagram showing the relationship between FIGS. 17a,
17b and 17c;
FIGS. 17a, 17b and 17c are a logic diagram illustrating the incrementer
adder, address gating circuit, ROM select circuit, upper and lower bute
transfer gates and the address multiplexer circuit for the ROM circuit;
FIG. 18 is a planar view of the CPU in integrated form;
FIG. 19 is a planar view of the ROM circuit in integrated form.
DETAILED DESCRIPTION
Referring now to the drawings and in particular to FIG. 1, a block diagram
of one embodiment of the microprocessor system of the present invention is
shown. The illustrated embodiment comprises two large scale integrated
circuit chips; the first of which is a Central Processing Unit (CPU) 20,
and the second is a Read Only Memory (ROM) circuit 22.
Voltage is supplied to the CPU 20 from one or more power supplies by means
of input lines 23. The CPU circuit 20 operates in response to an internal
oscillator having a frequency of operation determined by an RC circuit
comprising a resistor R10 and a Capacitor C10. Resistor R10 is coupled
between a source of positive voltage and a first input line 24 of the CPU
circuit 20. Capacitor C10 is coupled between the input line 24 and an
input line 26 of the CPU circuit 20. Line 26, for this particular circuit
configuration, is also coupled to ground potential. A third input line 28
is provided for use with a different type of external circuit for
oscillator reference that will be explained in greater detail hereinbelow.
Clock signals, which are generated within the CPU 20, are supplied to
additional circuits of the system (e.g., the ROM circuit 22) by means of
lines 29. These clock signals are employed for synchronizing the operation
of the complementary circuits (e.g., the ROM circuit 22) of the system
with the CPU 20 operation. An external reset signal is supplied to the CPU
20 by means of a line 30. The external reset signal, when supplied to the
CPU initiates operation at zero or the beginning address. A single
external reset signal supplied on line 30 resets the complementary
circuits as well as the CPU circuit. Normally, an external reset signal is
not required.
The CPU circuit has two input-and-output ports (hereafter called I/O ports)
31 and 32, which I/O ports are employed for receiving data from or
transmitting data to input-and-output devices (not shown). Each I/O port
in this embodiment is capable of receiving or transmitting 8-bits of data,
or an 8-bit byte. The CPU 20 also contains a random access memory (RAM)
33, which memory is employed by the CPU as a "scratch pad" memory while
performing computations and operations.
The CPU circuit 20 is coupled to the ROM circuit 22 by means of a data bus
34. The data bus 34 is also employed for transmitting data to and
receiving data from additional circuits (e.g., additional ROM circuits not
shown) that may be employed with the microprocessor system of the present
invention. In addition, a control bus 36 is coupled between the CPU
circuit 20 and the ROM circuit 22, which transmits control signals
generated within the CPU 20. The control bus 36 is also employed for
transmitting control signals to additional circuits (not shown) that may
be employed with the microprocessor system of the present invention. In
addition, two I/O ports 31 and 32, are provided in the ROM circuit 22.
Voltage is supplied to the ROM circuit 22 from one or more power supplies
by means of input lines 41.
The ROM circuit 22 contains a program counter 42 for sequentially
addressing a memory contained within the ROM circuit to effect retrieval
of program instruction codes stored in the memory. The program instruction
codes are used for directing operations of the microprocessor system.
Both the CPU 20 and the ROM circuit 22 have circuit provisions for
interrupting normal program operations when data is to be accepted from or
supplied to the input-and-output devices. In particular, the CPU 20
contains an interrupt circuit 44 and the ROM 22 circuit contain an
interrupt circuit 46. An interrupt priority-in signal is supplied from the
interrupt circuit 44 to the interrupt circuit 46 by means of a line 48.
The interrupt priority-in signal is generated within the CPU 20 and
operates to interrogate any interrupt requests which may exist within the
system. When an input/output device requests service for an input or
output operation, an interrupt service request signal is supplied from the
interrupt circuit 46 to the interrupt circuit 44 by means of a line 50.
The line 50 may also be connected to the interrupt circuits of additional
ROM circuits (not shown), which may be employed with the system of the
present invention.
An external interrupt signal may be supplied to the interrupt circuit 46 by
means of an input line 52. An interrupt priority-out signal is supplied on
a line 53 to other ROM circuits coupled to the system. An interrupt of the
system operation occurs under one of two conditions. First, an external
interrupt signal supplied on the line 52 in combination with an interrupt
priority-in signal supplied on line 48 generates an interrupt service
request signal on the line 50. Secondly, an interrupt priority-in signal
in combination with an output signal from an internal timer (not shown in
FIG. 1) will likewise generate an interrupt service request signal on the
line 50. This will be further explained hereinbelow. The interrupt service
request signal causes the CPU 20 to suspend normal operation and respond
to or service the request for an input or output operation.
In operation, the CPU 20 generates all the necessary control and timing
signals to operate the microprocessor system, and the CPU executes the
operations specified in the program instruction codes which are stored in
the ROM circuit 22. At least one memory circuit, such as the ROM circuit
22, is coupled to the CPU 20. The sequence of operations begins when the
CPU 20 transmits control signals on the control bus 36 to the ROM circuit
22. The control signals effect the retrieval of instruction codes from the
memory in the ROM circuit 22. The instruction codes thus retrieved are
transmitted by means of the data bus 34 to the CPU circuit 20 for decoding
and execution. The type of instruction code received by the CPU circuit 20
will determine the sequence of subsequent control signals transmitted on
the control bus 36 to other circuits for carrying out the specified
operations. Additional data may be retrieved from a memory, such as that
within the ROM circuit 22, or data may be received from an I/O port (such
as I/O ports 31, 32, 38 or 40) or output data may be supplied to one of
the I/O ports.
Referring now to FIG. 1a, an alternate type of external reference circuit
for the CPU oscillator is illustrated. In particular, input terminals 24,
26 and 28 of the CPU 20 may be coupled to a crystal oscillator circuit for
applications requiring a precise frequency of operation. A capacitor C12
is coupled between input lines 24 and 28, and input line 24 is coupled to
ground potential. A capacitor C14 is coupled between the input line 24 and
a circuit point 54. A crystal is coupled between circuit point 54 and
input line 28. Input line 26 is coupled directly to the circuit point 54.
Referring now to FIG. 2, a block diagram of the organization of the CPU
circuit 20 is shown. The input lines 24, 26 and 28, which are coupled to
an external reference circuit (FIGS. 1 and 1a), are connected to clock
circuits 56. The clock circuits generate two clock signals for all
circuits in the microprocessor system at a frequency determined by the
external reference circuit. In particular, the two clock signals are
supplied to all the CPU circuits by means of lines 58. For simplification
of the drawings, the lines 58 are not shown connected to the individual
circuits within the CPU 20. In addition, external clock signals are
supplied on the lines 29 from the clock circuits 56 for synchronizing
complementary circuits of the microprocessor system.
The data bus 34, which is coupled between the CPU 20 and the ROM circuit
22, is connected to an internal data bus 60 by means of a buffer circuit
62. The I/O ports 31 and 32 are coupled between I/O devices (not shown)
and the internal data bus 60. The internal data bus 60 is coupled in
parallel to an instruction register 64 by means of lines 65 and to a
transfer gate 66 by means of lines 67, respectively. The output of the
transfer gate 66 is coupled to a right multiplexer bus 68 by means of
lines 69. The instruction register 64 is coupled to the right multiplexer
bus 68 by means of lines 70, to the address input of the random access
memory 33 by means of lines 71, and to a sequential control circuit 72 by
means of lines 73.
In accordance with a preferred embodiment, data bus 34, internal data bus
60, and lines 65 and 67 each comprise 8 lines. The right multiplexer bus
68, and lines 69 and 70 each comprise 8 lines. The lines 71 coupling the
instruction register to the register 88 comprise 4 lines, whereas the
lines coupling the register 88 to the RAM 33 comprises 6 lines. The lines
73 coupling the instruction register 64 to the control circuit 72 comprise
16 lines.
The sequential control circuit 72, which essentially comprises a
programable logic array in this embodiment, decodes the program
instruction codes stored in the instruction register, and paces all the
system timing and data transfers for program execution. In particular, the
control circuit 72 comprises a state register and a control ROM. A typical
program logic array, which may be employed for the sequential control
circuit 72, is illustrated in greater detail in FIG. 3, and will be
described further hereinbelow. The contents of the instruction register 64
are supplied to the control circuit 72 by means of lines 73, and the CPU
20 timing and data transfer operations are paced by means of signals
supplied on lines 74 to all circuits within the CPU. The timing and data
transfer operations for the ROM circuit 22 and other complementary
circuits of the system are controlled by means of signals supplied from
the control circuit 72 on the line 36.
The interrupt logic 44 operates in response to the interrupt service
request signal supplied on the line 50. The output of the interrupt logic
44 is coupled to the control circuit 72 by means of a line 75. In
addition, the interrupt interrogate signal is supplied to the ROM 22 (and
other complementary circuits not shown) by means of the line 48. Signals
indicative of the state of the control circuit 72 are supplied to the
interrupt logic 44 by means of lines 77.
The external reset signal, which is supplied on the line 30, is applied to
the input of a power-on-detect circuit 76. The power-on-detect circuit
operates to initiate operation of the microprocessor system at zero or the
beginning address. In particular, a detection of "power up" causes the CPU
20 to disable the interrupt system and load the program counter 42 in the
ROM 22 with all zeros before execution of operation begins. An output
signal from the power-on-detect circuit 76, which indicates power up, is
supplied to the control circuit 72 by means of a line 78. In addition, a
signal supplied from the control circuit 72, which indicates a power-on
clear, is supplied to the power-on-detect circuit 76 by means of a line
79.
Arithmetic operations are performed in the CPU 20 by means of an arithmetic
logic unit 80 (ALU). Arithmetic logic units are well known in the art,
however the ALU used in this embodiment is illustrated in FIGS. 7a and 7b,
and will be explained further hereinbelow. The ALU employed in this
embodiment of the microprocessor system is a typical 8-bit parallel logic
network which has the capability of performing logical functions, and
operates in response to two operands. The first operand is supplied to ALU
80 from the right multiplexer bus 68 by means of lines 81. The second
operand is supplied to ALU 80 from a left multiplexer bus 82 by means of
lines 83. The output of the ALU 80 is supplied to a result bus 84 by means
of lines 85.
In this embodiment, the result bus 84 comprises 8 lines and transmits data
in the form of 8-bit bytes to the RAM 33 by means of lines 86; to an
indirect RAM address register 88 by means of lines 89; to an accumulator
register 90 by means of lines 91; to a status register 92 by means of
lines 93; and, to a transfer gate 94 by means of lines 95. The outputs of
the RAM 33 and the indirect RAM address register 88 are coupled to the
right multiplexer bus 68 by means of lines 95 and 97, respectively. The
outputs of the registers 90 and 92 are coupled to the left multiplexer bus
82 by means of lines 98 and 99, respectively. The output of the transfer
gate 94 is coupled to the internal data bus 60 by means of lines 100.
In operation, the sequence begins when the sequential control circuit 72
transmits the necessary control signals by means of the control bus 36 to
the ROM circuit 22 for retrieving an instruction code from the memory. The
instruction code is transmitted by means of the data bus 34 to the buffer
circuit 62, where the instruction code is gated onto the internal data bus
60. The instruction code is then loaded into the instruction register 64
by means of the lines 65. The status of the outputs of the instruction
register 64 are transmitted to the sequential control circuit 72 by means
of lines 73 for decoding. The resultant decoding establishes the control
sequence in executing the particular instruction code stored in the
instruction register. The sequential control circuit 72 transmits a
multiplicity of signals in a series of timing intervals to the
complementary circuits of the CPU 20 and the ROM circuit 22 by means of
the lines 36, 74 and 77. These control signals enable each of the
individual complementary circuits to function in a manner which completes
the particular instruction code specified by the binary contents stored in
the instruction register 74.
Typically, most instruction codes specify that two 8-bit bytes, also called
operands, are combined arithmetically in the ALU 80. A first of these two
operands is normally supplied from the accumulator register 90, and
transmitted to the ALU 80 by means of lines 98, left multiplexer bus 82
and lines 83. The second operand is usually supplied from one of several
sources as determined by the instruction code stored in the instruction
register 64. For example, the second operand may be supplied from the RAM
33, the indirect RAM address register 88, or external data supplied by
means of the internal data bus 60 and the transfer gate 66. The ALU 80
combines the two operands supplied from the left multiplexer bus 82 and
the right multiplexer bus 68 by means of lines 83 and 81, respectively,
and derives a result which is transmitted to the result bus 84 by means of
the lines 85. The result derived in the ALU 80 may be stored in the RAM
33, the indirect RAM address register 88, the accumulator register 90, the
status register 92, or it may be supplied to external circuits by means of
the transfer gate 94, and I/O port or the buffer 62.
If the second operand is to be supplied by the RAM 33, an address code is
supplied to the RAM 33 from either the indirect RAM address register 88 or
the four least significant bits of the instruction register 64 by means of
the lines 71. The instruction code stored in the instruction register 64,
which is decoded by the sequential control circuit 72, determines which of
the two sources of the RAM 33 address is to be used.
In some of the instruction codes to be executed by the CPU 20, the ALU 80
generates status information concerning the nature of the results supplied
at the output of the ALU 80 on the lines 85. This status information is
transmitted to the status register 92 by means of lines (not shown), which
will be described further hereinbelow, and is stored in the status
register for future use in response to subsequent instruction codes.
Output instruction codes, which are frequently employed, direct the
transfer of the contents of the accumulator register 90 to a particular
I/O port, or to the data bus 34 by means of the buffer 62. The output
instruction code contains an address that designates which of the I/O
ports or the buffer 62 is to receive the contents of the register 90. In
particular, the sequential control circuit 72 initially generates the
required control signals and supplies these signals on the lines 36 to the
ROM circuit 22. The control signals direct the retrieval of the next
instruction code (hereof, output instruction) from the memory within the
ROM circuit 22. The instruction code thus retrieved is transmitted by
means of the data bus 34, through the buffer 62 to the internal data bus
60 for storage in the instruction register 64. The output instruction code
is supplied to the sequential control circuit 72 by means of the lines 73
for decoding. The sequential control circuit 72 decodes the output
instruction code, and in response thereto transmits the required control
signals on the lines 74 to effect the connection of internal data paths
between the accumulator registor 90 and the address I/O port or buffer 62.
The internal data path is from the output of the accumulator register 90
to the left multiplexer bus 82 by means of the lines 98, through the ALU
80 to the result bus 84 without modification, through the transfer gate 94
to the internal data bus 60, and then to the addressed I/O port or buffer
62. The I/O ports employed in the present invention are adapted for
storing an 8-bit byte of data by means of latches which will be explained
in greater detail hereinbelow.
Input instruction codes, which are also frequently employed, direct the
transfer of an 8-bit byte of data from an I/O port to the accumulator
register 90. The input instruction code is retrieved from the memory in
the ROM circuit 22 in the same manner as described above for retrieval of
the output instruction code. The sequential control circuit 72 transmits
control signals on the lines 74, which subsequently address an I/O port to
accept data from the external I/O device. Data received by an I/O port
(e.g., I/O port 31 or 32) is transmitted along the internal data bus 60,
through the transfer gate 66, along the right multiplexer bus 68, through
the ALU 80 without modification, along the result bus 84, and finally to
the accumulator register 90 for storage.
In summary, each of the instruction codes for the microprocessor of the
present invention effect unique system functions in a manner similar to
that described above. The sequence of operation always begins with the
retrieval of the next instruction code to be executed from the ROM circuit
22, and the storing of this instruction code in the instruction register
for decoding and execution thereof. The instruction code is always decoded
by the sequential circuit 72, whereupon the system control signals are
derived and transmitted to the complementary circuits of both the CPU 20
and the ROM 22 circuits by means of the lines 36, 74, and 77. The control
signals activate the complementary circuits in such a way as to complete
the operation called for by the instruction code. At the completion of
each instruction code, the sequential control circuit 72 transmits control
signals on the lines 36 to direct the retrieval of the next instruction
code to be decoded and executed. Thus, a specific microprocessor system
operation can be implemented by storing in advance a sequence of
instruction codes in the ROM circuit 22, wherein the order of the
instruction codes determines the system function to be performed.
In the detailed description that follows, the individual circuits of the
CPU 20, as delineated by the blocks in FIG. 2, are described in greater
detail. In addition, a block diagram showing the organization of the ROM
circuit 22 is illustrated in FIG. 11 and described hereinbelow, which is
followed by a detailed illustration and description of the individual
circuits of the ROM circuit.
Referring now to FIG. 2a, a combined logic-block diagram of the clock
circuits 56 is illustrated. Input terminals 24, 26 and 28 are coupled to
an oscillator and clock logic 1300. The oscillator 1300 has a preferred
operating range from 500 kilohertz to 2 megahertz. Two clock signals are
supplied from the oscillator 1300 on lines 1301 and 1302, respectively.
The lines 1301 and 1302 are coupled to the C.sub.1 and C.sub.2 inputs of
flip-flops 1304, 1305 and 1306. The true (Q) output of the flip-flop 1304
is coupled to the first of three inverted inputs of an AND gate 1308, to
the first of four inverted inputs of an AND gate 1309, to the first of two
inputs of a NOR gate 1310, and to the first of three inverted inputs of an
AND gate 1311. The true (Q) output of the flip-flop 1305 is coupled to a
second inverted input of the AND gate 1309, and to the input of an
inverter 1312. The output of the inverter 1312 is coupled to the "D" input
of the flip-flop 1306, to a second inverted input of the AND gate 1311,
and to a second inverted input of the AND gate 1308. The true (Q) output
of the flip-flop 1306 is coupled to the third inverted inputs of the AND
gates 1308 and 1309. The not true (Q) of the flip-flop 1306 is coupled to
the third inverted input of the AND gate 1311.
The fourth inverted input of the AND gate 1309 is coupled to a line 74af
from the control circuit 72. The signal supplied on the line 74af operates
to cause the clock circuits to count six clock signals per machine cycle
in lieu of the four clock signals per machine cycle normally employed. The
output of the AND gate 1308 is coupled to the first of two inputs of an OR
gate 1313. The output of the AND gate 1309 is coupled to the second input
of the OR gate 1313 and to the second input of the NOR gate 1310.
The output of the AND gate 1311 is coupled to the input of an inverter
1314, and to the input of an amplifier-driver 1315. The output of the
amplifier-driver 1315 is coupled to the line 29b, which transmits a first
synchronization signal to complementary circuits (e.g., ROM circuit 22) of
the system. The output of the inverter 1314 is coupled to the input of an
inverter 1316, and to the first of two inverted inputs of an AND gate
1318. The output of the inverter 1316 is coupled to the first of two
inverted inputs of an AND gate 1320. The output of the AND gate 1320 is
coupled to a line 58a of the lines 58 (FIG. 2), and to the second inverted
input of the AND gate 1318. The output of the AND gate 1318 is coupled to
a line 58b, and to the second inverted input of the AND gate 1320.
A single clock signal is generated by the oscillator (not shown) within the
oscillator and clock logic 1300 which is employed for generating the two
complementary clock signals supplied on the lines 1301 and 1302. The
single clock signal from the oscillator is supplied to the input of an
amplifier-driver 1322. The output of the amplifier-driver 1322 is coupled
to the line 29a, which transmits a second synchronization signal to the
complementary circuits of the system.
Referring now to FIG. 2b, a timing diagram of the circuit illustrated in
FIG. 2a is illustrated. Waveform 1330 represents the single clock signal
generated by the oscillator (not shown) in the oscillator and clock logic
1300. Waveform 1330 also represents the second synchronization signal
supplied on the line 29a through the amplifier-driver 1322 (FIG. 2a).
Waveforms 1331 and 1332 represent the clock signals supplied on the lines
1301 and 1302, respectively. Waveform 1333 represents the signal appearing
at the output of the AND gate 1311, and the first synchronization signal
supplied on the line 29b. Waveforms 1334 and 1335 represent the clock
signals supplied on the lines 58a and 58b, respectively.
The frequency of the clock signals supplied on the lines 58a and 58b can be
changed as a result of a signal supplied on the line 74af. When a low
level signal is supplied on the line 74af six cycles of the clock signals
as represented by the waveforms 1331 and 1332 are required to generate a
single cycle of the clock signals to be supplied on the lines 58a and 58b
(i.e., waveforms 1334 and 1335) in lieu of the four cycles normally
required as illustrated.
Referring now to FIG. 3, the organization of the sequential control circuit
72, and connections to the instruction register 64 are illustrated in
greater detail. In one embodiment, instruction register 64 comprises 8
flip-flops where each of the lines 65 are connected to corresponding data
("D") inputs of each of the 8 flip-flops, respectively. The lines 73 which
are connected between the instruction register 64 and the sequential
control circuit 72 are connected to a portion of the address input of the
Read Only Memory (ROM) 102. Both the true and not true outputs of each
flip-flop within the register 64 are connected to the address input of ROM
102. The true output of the low-order four flip-flops of register 64
comprise the lines 71. Two clock signals are supplied to the clock inputs
of the register 64 by means of the lines 58 (FIG. 2).
The clock signals supplied on the lines 58 are also connected to the clock
inputs of a state register 106. State register 106 comprises four
flip-flops having both the true and not true output terminals coupled to a
portion of the address input of the ROM 102. Four output terminals of the
ROM 102 are coupled to the input terminals of the four flip-flops within
the register 106 by means of lines 108. The lines 108 comprise the state
lines for the sequential control circuit 72, and indicate the last state
of the circuit 72 (or a portion of the last output code of the ROM 102).
The three low-order positions of the lines 108 comprise the lines 77,
which are coupled to the input of the interrupt logic 44 and to the
instruction register 64 (FIG. 2). The line 75 from the interrupt logic 44
is coupled to the high-order position of the state register 106 to
preclude setting the high-order flip-flop under certain interrupt
conditions to be explained in greater detail hereinbelow.
Four additional address input signals are supplied to the ROM 102 by means
of lines 110 and 112 in combination with inverters 114 and 116. Line 110
is coupled, by means of logic circuits, across the result bus 84, and the
inverter 114 inverts the signal supplied from the result bus 84, thereby
simultaneously providing both the true and the complement of this signal
to the ROM 102 input address. The signal supplied on the line 112 is
provided by the indirect RAM address register 88. In a similar manner,
inverter 116 inverts the signal supplied on the line 112, thereby
providing simultaneously both the true and the complement of this signal
to the ROM 102 address input. The five lines 36, which transmit the
control signals to the complementary circuitry of the system, are coupled
to output terminals of the ROM 102. The lines 74, which transmit control
signals to the complementary circuitry within the CPU, are coupled to the
remaining output terminals of the ROM 102.
The ROM 102 is a typical read-only memory well known in the prior art. The
ROM 102 comprises a multiplicity of cells arranged in groups, which cells
store binary digits (zero or one). Each group of cells stores a unique
binary number. When an address for a specific group of cells is provided
at the address input of the ROM 102, the binary number stored in that
group of cells is supplied at the output thereof (lines 36, 74 and 108).
With reference to the system of the present invention, each binary number
stored within each gro | | |
