Tracking digital angle encoder - Patent Review 3984831

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BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a digital angle encoder and more particularly to a tracking digital angle encoder which utilizes a resolver, a translator, a threshold detector and a counter.

2. Description of the Prior Art

Prior art digital angle encoders utilize multiple gear discs in an arrangement where each disc is read by a device such as a light emitting diode and a phototransistor arrangement. Experience has shown in many industrial applications that vibration and handling of prior art encoders has caused substantial maintenance and down time. Prior art digital angle encoders also are capable of only providing a discrete indication of the shaft position. That is, they cannot indicate the shaft position continuously over its entire rotation with essentially infinite resolution.

An absolute digital position encoder cannot provide a continuous indication of the shaft position. That is, the prior art digital encoders must necessarily break the shaft position down into a discrete number of intervals or angles. Once selected, the size of these intervals or angles cannot be adjusted, and also, the movement or position of the shaft within each discrete interval is indeterminable. Since the interval or angle cannot be adjusted, the digital counts corresponding to a given rotation are fixed. Whenever the term resolver is utilized herein, it is understood to mean resolver, synchro, differential transformer, control transformer or any other sinusoidal position indicating device. The output of resolvers are normally in suppressed carrier form, but it is customary to discuss the output as representing the cosine and sine of selected analog angles. Whenever sine and cosine functions are discussed herein, it is to be understood that these can represent signals in absolute or suppressed carrier form.

U.S. Pat. No. 3,609,320 describes a digital measuring system whereby the position of a movable member is measured utilizing a multiple counter technique which develops sine and cosine signals in Pulse Width Modulated form for application to a trigonometric type angle transducer. An error signal is generated by the transducer to control various logic subsystems that direct the counting of certain counters. The system uses a position measuring device having a plurality of operating cycles for generating an error signal as a function of the position of the movable member relative to the workpiece.

U.S. Pat. No. 3,686,487 also describes a digital measuring system that employs trigonometric signal generators. The system includes a digital to analog converter method to generate two or more analog output signals as a function of a digital input. The analog outputs which are Pulse Width Modulated rectangular waveforms include a fundamental sinusoidal frequency component having an amplitude proportional to a trigonometric function of the digital input. The analog outputs are typically connected as inputs to a position measuring device to trigonometrically define the position between two members of the position measuring transducer.

Like U.S. Pat. No. 3,609,320, the system of the 3,686,487 patent employs the position measuring device as an angle receiver, accepting Pulse Width Modulated signals derived from the array of electronic circuits.

SUMMARY OF THE INVENTION

A tracking digital angle encoder is provided which utilizes a translator, for providing the difference between an analog position input and a digital position input, and a detector which controls a counter providing the digital position input to the translator so that the digital input is counted to a position where the output of the translator is held to a predetermined small value. Thus, the digital position input is equal to the analog position input, with at most a difference error of one digital count. That is, the digital output of the BCD counter represents a position which is within one of the least significant bits (LSB) to the absolute position represented by the analog input. The detector activates either of two gates permitting clock pulses to pass to the appropriate input of the up/down counter so that the digital output of the counter follows the analog input to the translator. The frequency of the clock pulse can, if desired, be made dependent on the difference between the digital output of the counter and the analog input to the translator. That is, the clock frequency can be varied in steps or continuously as the output of the digital counter approaches the analog input to the translator.

The analog input to the translator can be in sine, cosine form from a resolver, in which case the digital angle output of the counter will follow or track the position of the resolver. The output of the resolver can be in suppressed carrier form and the analog output of the translator will also be in suppressed carrier form. The output of the translator can be fed to a balance demodulator whose excitation is the same as the carrier and the envelope of the demodulated signal is actually proportional to the difference between the analog and digital inputs to the translator. Using this analog error signal, a continuous tracking resolver to digital angle converter can be constructed.

The detector can also be interconnected with the output of the reference oscillator which feeds the resolver, so that any variation in the resolver output due to the oscillator will be compensated for.

The demodulated error signal is fed to a double ended threshold detector whose upper and lower thresholds are set at equivalent DC levels of plus 1/2 of the value of the least significant bit (LSB) and minus 1/2 of the value of the least significant bit (LSB). For example, if a 360.degree. circle is divided into a thousand parts, where each part is equivalent to .36.degree., the threshold detector would be set at values approximately equivalent to +.18.degree. and -.18.degree.. In practice the threshold levels are set at equivalent DC levels of slightly greater than plus 1/2 LSB and slightly more negative than minus 1/2 LSB, to guarantee stability. Hereafter the threshold levels will be referred to as plus 1/2 LSB or minus 1/2 LSB, or their angular equivalents, for convenience. Whenever the output of the translator is greater than +.18.degree., the upper threshold of the detector will activate a gate enabling the binary coded decimal (BCD) up/down counter to count up. Similarly, whenever the output of the translator is less than -.18.degree., the lower threshold detector will enable the up/down counter to count down. When the output of the translator is between values equivalent to +.18.degree. and -.18.degree., the clock pulses to the up/down counter are inhibited and the counter indicates approximately the digital equivalent of the analog angular input to the translator. The tendency of the counter is to reach a steady state with a minimum error signal. In the disclosed tracking digital angle encoder, the counter output reaches a steady state when the demodulated error signal drops to a value within .+-. 1/2 of the least significant bit. Steady state output of the digital counter, which is in binary coded decimal form, corresponds to the analog angular input within an angle equivalent to the value of the least significant bit.

If the resolver shaft is rotated to a new position, the threshold detector instantaneously will enable the clock pulses to move the counter output in the right direction until the error signal drops to within essentially plus or minus 1/2 of the least significant bit; and, the counter output will settle to a new steady state value equal to the BCD equivalent of the new resolver angular position. The tracking nature of the converter can easily be understood from the above information. To keep the settling time for the counter small, a high clock frequency must be used. As explained above, the clock frequency can be varied as the settling or null point is approached.

The teaching of U.S. Pat. No. 3,609,320 can be contrasted with the system described in the instant application which does not utilize the position measuring device for the generation of the error signal, but incorporates an angle translator which generates the position error signal as a function of the absolute angular input from the position measuring device and an absolute digital input which is generated by the internal circuitry.

Furthermore, the instant application discloses a system that measures the absolute position of a mechanism and teaches the use of a plurality of such systems that can be employed to measure the absolute position over multiple revolutions or electrical cycles of any one of the measurement transducers.

The advantage of measuring the absolute position over the full range of travel is obvious, since with an absolute system the readout of position is always exact even if the mechanism to be measured is moved while the power to the electronic measuring system is removed and then reapplied. For the incremental system described in U.S. Pat. No. 3,609,320, removal of power will cause the counters to lose their memory and therefore not be able to indicate exact position when the power is reapplied.

A device constructed according to the teaching of the invention of the instant application incorporates a novel translator and associated circuits that do not require the generation of two precise analog outputs. Instead, the translator accepts the analog outputs of the position measuring device directly and incorporates only one counter to provide a digital output representative of the position of the measuring device. Furthermore, additional novel techniques have been added to vary the equivalency between the output of the position measuring device and the digital output of the system which can be varied either from an external signal or as a predetermined function of the digital output.

Prior art tracking digital angle encoders cannot differentiate between any two positions of the resolver which are 180.degree. apart when power is initially turned on. To overcome this difficulty the resolver output corresponding to the minus cosine of the analog angular input is demodulated and used for switching the counter to its midpoint when power is applied and the cosine value is negative. Since the cosine of the analog angular input is negative for analog angles between 90.degree. and 270.degree. this factor is utilized to preset the counter to its midpoint, which for a thousand count counter would be 500, whenever the resolver shaft is setting at an angle between 90.degree. and 270.degree., and to 000 otherwise. As soon as the counter is set, when power is applied, the tracking action of the digital angle encoder takes over and the counter output settles to the correct value within approximately plus or minus 1/2 of the least significant bit. Utilizing the cosine to position the counter at either 0 or its midpoint when power is applied reduces the time required for the counter to indicate the position of the resolver.

The disclosed tracking digital angle encoder also utilizes an adjustment disposed between the detector and the counter output, which permits the threshold level at which the detector activates to be varied. This adjustment allows the number of counts corresponding to full rotation of the resolver input shaft to be varied. That is, each count of the counter corresponds to a known angular rotation of the resolver shaft; by adjusting the level of threshold detector the value of the angle to which each bit of the counter corresponds can be varied. This option allows for errors due to mechanical tolerances, mechanical wear, or nonuniform mechanical adaptions to be easily corrected.

The threshold detector levels can be derived from the reference oscillator, by a rectifying circuit which sets the fundamental threshold levels as a function of the amplitude of the reference oscillator. Thus, if the reference oscillator amplitude changes, the threshold detector levels will automatically change accordingly. This prevents changes in the amplitude of the reference oscillator from affecting the output of the digital counter. Signals can be added at various points in the encoder circuit to vary the output of the digital counter or to vary the detector levels. This can be useful for rejecting unwanted signals or to compensate for linear or non-linear errors.

It is an object of this invention to provide a digital angle encoding system that also includes an analog output, with essentially infinite resolution, proportional to shaft movement over any section of the shaft rotation.

It is an object of this invention to provide a tracking digital angle encoder which utilizes a resolver which provides a continuous analog angular output, a translator, a detector and a counter.

It is a further object of this invention to provide a tracking digital angle encoder wherein the angular value represented by each count of the digital counter can be varied.

It is a still further object of this invention to provide a tracking digital angle encoder which positions the counter at 0 when the angular position of the shaft is in the first or fourth quadrant and positions the counter at its midpoint when the angular position of the shaft is in the second or third quadrant.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the invention, reference may be had to the preferred embodiments exemplary of the invention shown in the accompanying drawings in which:

FIG. 1 is a diagram of an analog to digital angle encoder utilizing the teaching of the present invention;

FIG. 2 is a block diagram of a tracking digital angle encoder utilizing the teaching of the present invention;

FIG. 3 is a block diagram of an absolute positioning servo system utilizing the digital angle encoder shown in FIG. 1;

FIG. 4 is a diagram of an absolute positioning servo system utilizing the digital angle encoder illustrated in FIG. 2;

FIG. 5 is a graph showing the variation of the modulated error signal with respect to position;

FIG. 6 is a block diagram of a prior art servo positioning system; and

FIG. 7 is a preferred embodiment of a portion of the encoder circuit shown in FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the drawings and FIGS. 1 and 2 in particular, there is shown a digital angle encoder 10 utilizing the teaching of the present invention. As is shown in FIG. 1 an analog signal .theta., which represents a position, is fed to one input of a translator 12, while a digital signal .phi. is fed to another input of translator 12. Translator 12 provides an output (.theta. - .phi.) which is equivalent to the difference between its inputs. This difference (.theta. - .phi.) is fed to a detector 14 which determines if the (.theta. - .phi.) error signal is positive or negative and activates appropriate AND gate 16 or 18 so that a clock 20 can activate counter 22 to reduce the error signal (.theta. - .phi.) to within a predetermined value. That is, counter 22 counts so that (.theta. - .phi.) at steady state it is within one count of the least significant bit to .phi.. For example, for a one thousand count counter, each count is equal to .36.degree. and the digital output .phi. of counter 22 will be within .36.degree. of the analog input .theta.. That is, if every indication .phi. of counter 22 is viewed as representing an absolute point, then the analog input .theta. is within plus or minus 1/2 of the least significant bit to that point. For a one thousand count counter then, the analog signal .theta. is within .18.degree. of an absolute point, which in realty, is the midpoint of the range defined by the counter indication .phi.. Detector 14 is constructed so that whenever (.theta. - .phi.) is greater than plus .18.degree. by a small amount, the detector 14 will activate AND gate 16 to enable up/down counter 22 to count up, increasing .phi., in response to pulses from clock 20. Similarly whenever (.theta. - .phi.) is less than -.18.degree. by a small amount, the lower threshold AND gate 18 will be activated enabling the counter 22 to count down, decreasing .phi., in response to pulses from clock 20. However, when the absolute value of (.theta. - .phi.) is less than .18.degree. both the up and down gates 16 and 18, respectively, are disabled and clock pulses are not fed to the counter. Whenever the error signal is positive, the counter counts up. Similarly whenever the error signal is negative, the counter counts down. The output of the counter, which is normally in binary coded decimal form (BCD), is fed back to the translator 12 along line 24. In essence, this is a closed loop feedback control system. The disclosed system is an electronic servo, wherein the digital output of counter 22 follows the analog input to translator 12. The tendency of the system is to reach a steady state with minimum error signal. If the analog input angle .theta. is arbitrarily changed to a new position, detector 14 instantly will enable the proper AND gate 16 or 18 to clock the counter in the right direction until the error signal (.theta. - .phi.) drops to within the range plus or minus 1/2 of the least significant bit (LSB) and the counter output 22 will settle to a new steady state value equal to the best BCD equivalent of the new analog indication.

The disclosed analog to digital angle encoder 10 preferably utilizes a solid state translator as described in more detail in copending U.S. Pat. application Ser. No. 529,701. Translator 12 can best be described as a hybrid computer which performs the computation of the function sin (.theta. - .phi.); where .theta. is the angular position of a resolver 30 and .phi. is the angle of the counter 22.

Referring now to FIG. 2, there is shown a tracking digital angle encoder 10 utilizing the teaching of the present invention. Translator 12 is fed an analog signal .theta. which is in suppressed carrier sine, cosine form. A resolver 30 provides a signal K.sub.1 E sin .theta. sin .omega.t on line 31 and the signal K.sub.1 E cosin .theta. sin .omega.t on line 32 which are fed to translator 12. Sin .omega.t is a carrier the magnitude of whose envelope provides the desired information. Another input, in digital or in binary coded decimal (BCD) form, is provided to the translator 12 from counter 22 along line 33. If desired, an optical display 34 of the output of digital counter 22 can be provided. The output 34 is controlled by the position of the shaft of resolver 30 as will be hereinafter described in detail. The output of display 34 is the digital equivalent of the analog input to translator 12. Thus the output of the display 34 provides a visual indication of the position of the resolver shaft 30. Translator 12 provides an output equal to sin (.theta. - .phi.) sin .omega.t. The analog function sin (.theta. - .phi.) sin .omega.t is generated by performing certain trigonometric manipulations on the resolver output signals sin .theta. sin .omega.t and cos .theta. sin .omega.t and is based on the following identity:

sin (.theta. - .phi.) = (sin .theta. - cos .theta. tan .phi.).sup.. cos .phi.. The programmed angle .phi. is usually available as a 12-bit BCD (3 decade) word. With the addition of a few other building blocks, a continuous tracking resolver to digital angle encoder can be constructed. For a thousand count counter, the digital angle encoder will have a range of 0 to 999 plus or minus 1/2 LSB (0.degree. - 359.64 plus or minus .18.degree.). The output of the translator 12 is an amplitude modulated sine wave proportional to sin (.theta. - .phi.) sin .omega.t. This output signal is fed to a balanced demodulator whose excitation is the same as the carrier E sin .omega.t. The output of the demodulator is proportional to sin (.theta. - .phi.), with the carrier removed. This represents the differential error between the resolver angular position .theta. and the digital position .phi. from counter 22. When .theta. is approximately equal to .phi., then sin (.theta. - .phi.) is approximately equal to (.theta. - .phi.). Demodulated error signal sin (.theta. - .phi.) is fed to a double ended threshold detector 15 whose upper and lower threshold limits are set at essentially DC levels of +1/2 LSB and -1/2 LSB, respectively. Expressed in degrees, the threshold levels are equivalent to +.18.degree. and -.18.degree., for a one thousand count counter. Whenever (.theta. - .phi.) is greater than +.18.degree. the upper threshold detector will switch and enable preset BCD up/down counter 22 to count up. Similarly, whenever (.theta. - .phi.) is less than -.18.degree., the lower threshold detector will enable the counter 22 to count down. However, when absolute value (.theta. - .phi.) is less than .18.degree., both the up and down counter lines 17 and 19, respectively, are disabled and the clock pulses are inhibited to the counter 22. The phasing of the demodulator is such that whenever the error signal is positive the counter counts up. Similarly when the error signal is negative, it counts down. Counter output word .phi. is coupled back to translator 12. The tendency of the system is to reach a steady state with minimum error signal. In the disclosed system the counter output reaches a steady state when the demodulated error signal drops down to a value within plus or minus 1/2 LSB. In the steady state the counter output word .phi. will be the BCD number corresponding to .theta. within plus or minus 1/2 LSB.

If the resolver 30 shaft is arbitrarily rotated to a new position, the threshold detector 14 instantaneously will enable the clock pulses to clock the counter 22 in the proper direction, until the error signal drops to within plus or minus 1/2 LSB and the counter 22 output will settle to a new steady state value equal to the BCD equivalent of the new resolver 30 angular position. From the above explanation, it can be easily seen that when the resolver 30 is rotated to a new position, the digital output of the counter 22 will follow; thus the tracking nature of the system is obvious.

To keep the settling time, that is the time for the counter 22 output digital word to settle to a new value after a change in the resolver 30 shaft position, small, a high clock frequency is used. The period of the clock cycle, however, should be sufficiently greater than the turn on time for the solid state analog switches utilizes in the system. For the tracking digital angle encoder shown in FIG. 2 a clock frequency of 100 KHz is used. The frequency of clock 20 can vary as the new settling position is approached. The variation can be continuous or in discrete steps. The output of translator 12 (.theta. - .phi.) can be se