An arrangement for determining the phase position between two signals includes a circuit containing a gate with two inputs for the signals and an output for a first output signal which is dependent on the phase position between the input signals. A flip-flop has an input for one of the input signals and a second input for the first output signal. The second input of the flip-flop contains a time-delay circuit for the first output signal. Two similar circuits can be used.
A sawtooth phase comparator comprising a bistable flip-flop is provided with a controlled 180.degree. phase-shifter on one input so that a phase shift is carried out when the time between successive SET- and RESET pulses to the flip-flop is less than a given time, thereby improving the linearity of the output characteristic of the comparator.
A digital phase sequence detector which operates completely independent of signal amplitude values to provide an output signal having a logic level indicative of which of two phasors being compared is leading. The detector develops first and second feedback signals which determine the stable state of the circuit. This feedback arrangement enables the detector to be constructed of standard integrated circuits devoid of flip-flops or other memory elements requiring a clock. The level of the output signal of the detector persists for as long as the relationship being indicated persists, eliminating the need for pulse stretchers, timers, or the like.
A flip-flop having a reset preferential function, comprising a set input terminal, a reset input terminal, a clock signal source operatively coupled through a field effect transistor to the set input terminal, a capacitance formed at the gate electrode of the field effect transistor, a charge control transistor controllable responsive to the clock signal for precharging the capacitance prior to the clock signal, a discharge control transistor controllable responsive to the reset signal for discharging the capacitance, whereby the capacitance is precharged prior to the clock signal and is discharged responsive to the reset signal, the field effect transistor being rendered conductive as a function of the electric charge of the capacitance, the clock signal source being operatively coupled to the set input terminal as a function of the conduction state of the field effect transistor, whereby the flip-flop is set responsive to the leading edge of the clock signal and is reset responsive to the reset signal in preference to the clock signal.
