Improved features for a fabrication arrangement that reduces the number of LSI chips required in a bit stream measurement system comprised of a plurality of measurement elements, each element including a large programmable array. The improvements are on the basic fabrication arrangement of patent application Ser. No. 482,824. The improvements relate the chip and measurement element fabrication to the detection significance of parts of the bit stream by substituting delay shift registers for array portions to handle the less significant parts of the bit stream in some measurement elements. The detection operations can then be concentrated on the more significant parts of a bit stream, such as the part representing the top, bottom, left or right portion of an optical character recognition machines bit stream represented character frame. The resulting modifications in chip and element fabrication result in a further reduction in the average number of chips required in the measurement system. The LSI array chips can be identically made.
A programmable logic device (PLD) is disclosed which can efficiently, in a real estate sense, emulate a Mealy state machine. Specifically, there is a PLD which has: (1) a programmable logical AND and two programmable logical OR arrays, similar to a field programmable logic array; and (2) one of the two fully programmable OR array generates a next state of the circuit and the second OR array generates an output responsive to both the inputs and the current state.
A programmable logic device (PLD) is disclosed for finding a sum of products or other logic equations. Specifically, there is a PLD which has: 1) a programmable logical AND and programmable logical OR arrays/matrices, similar to a field programmable logic array; and 2) the fully programmable OR array has an optimized signal speed path and non-optimized signal speed path.
A programmable logic device (PLD) with an output macrocell circuit is disclosed. Specifically, there is a macrocell having an exclusive logic signal feedback line and an exclusive external input signal line both feeding into the input of the PLD. Exactly, this PLD can disable the I/O pad and still have an internal feedback to its logic circuitry.
A programmable logic device (PLD) with an output macrocell circuit is disclosed. Specifically, there is a field programmable logic array (FPLA) using a dedicated product term for macrocell control. Particularly, the macrocells contain a faster, more flexible, and exclusive feedback line as well as an exclusive external-input line from an input/output (I/O) pad for a registered mode of operation. Moreover, there is a registered mode macrocell which has 1) a feedback path for the registered mode signals which is activated even when the I/O pad driver is disabled, 2) an input path, to the logic circuitry, over an I/O pad, 3) a feedback path for the registered mode signals while outputting the same registered mode signals, and 4) a feedback path which avoids the unnecessary signal noise emanating from the use of a 3-state device or output driver. In addition, the macrocell allows for a disabled tri-state and still have the feedback intact for the combinatorial mode; thus, avoiding the extra noise that a tri-state creates.
A programmable logic device (PLD) is disclosed which has an output macrocell. The macrocell selectively produces either a registered and inverted registered set of signals, or a combinatorial or inverted combinatorial set of signals, but not both set of signals.
