Electronic computer with equipment for debugging operative programs

What I claim is:

1. An electronic computer with equipment for debugging operative programs comprising:

a first memory for storing instructions and data of said operative programs;

a central unit for processing said programs;

a switching element normally having a first state for defining a first mode of operation of said computer for processing said operative programs and a second state for defining a second mode of operation for processing a debugging program for debugging said operative programs;

a keyboard for entering into said first memory information relating to said operative programs during said first mode of operation;

first means controlled by the switching of said switching element from said first state into said second state to interrupt said first mode of operation and to activate said second mode of operation, second means controlled by the switching of said switching element from said first state to said second state to store the parameters needed to subsequently restart execution of said operative program from the point of interruption,

third means responsive to the second state of said switching element to enable said keyboard to enter into said first memory information to be processed by said debugging program,

fourth means controlled by the switching of said switching element from said second state to said first state and responsive to said stored parameters for automatically restarting said operative program, whereby the switching between said modes of operation does not need any intervention by the operator for the correct restart of the operative program.

2. A computer according to claim 1, wherein said switching element is manually operable.

3. An electronic computer with equipment for debugging operative programs comprising:

a first memory for storing instructions and data of said operative programs;

a central unit for processing said programs;

a switching element normally having a first state for defining a first mode of operation of said computer for processing said operative programs and a second state for defining a second mode of operation for processing a debugging program for debugging said operative programs;

a keyboard for entering into said first memory information relating to said operative programs during said first mode of operation;

a display unit for displaying information relating to said operative programs during said first mode of operation;

first means controlled by the switching of said switching element from said first state into said second state to interrupt said first mode of operation and to activate said second mode of operation;

second means controlled by the switching of said switching element from said first state to said second state to store the parameters needed to subsequently restart execution of said operative program from the point of interruption,

third means responsive to the second state of said switching element to enable said keyboard to enter information to be processed by said debugging program;

fourth means responsive to the second state of said switching element to enable said display unit to display information relating to said debugging program,

fifth means controlled by the switching of said switching element from said second state to said first state and responsive to said stored parameters for automatically restarting said operative program, whereby the switching between said modes of operation does not need any intervention by the operator for the correct restart of the operative program.

4. A computer according to claim 3, wherein said fourth means comprises transmitting means responsive to said switching element to cause during said second mode of operation said central unit to transmit to said display unit the address of the next instruction of said operative program to be executed and coding means for generating a coding of the information located at said address and for supplying said coding to said display unit.

5. A computer according to claim 4 further comprising:

a condition program register for storing at least one of said parameters including significant results of previously performed instructions,

said fourth means comprising:

means conditioned by said switching element to send to said display unit during said second mode of operation the information stored in said condition program register.

6. A computer according to claim 3, wherein said switching element is manually operable.

7. An electronic computer with equipment for debugging operative programs comprising:

a first memory for storing instructions and data of said operative programs:

a central unit for processing said programs;

a switching element normally having a first state for defining a first mode of operation of said computer for processing said operative programs and a second state for defining a second mode of operation for a debugging program for debugging said operative programs;

said debugging program comprising a plurality of blocks;

a keyboard having a plurality of keys for entering into said first memory information relating to said operative programs during said first mode of operation;

first means controlled by the switching of said switching element from said first state into said second state to interrupt said first mode of operation and to activate said second mode of operation;

second means controlled by the switching of said switching element from said first state to said second state to store the parameters needed to subsequently restart execution of said operative program from the point of interruption,

third means responsive to the second state of said switching element to enable said keyboard to enter into said first memory information to be processed by said debugging program;

fourth means controlled by said switching element during said second mode of operation to associate a group of predetermined keys of said plurality to a corresponding block of said debugging program and to cause said central unit to selectively activate each of said blocks for processing information introduced from said keyboard before the actuation of one key of said group;

fifth means controlled by the switching of said switching element from said second state to said first state and responsive to said stored parameters for automatically restarting said operative program, whereby the switching between said modes of operation does not need any intervention by the operator for the correct restart of the operative program.

8. An electronic computer with equipment for debugging operative programs comprising:

a first memory for storing instructions and data of said operative programs;

a central unit for processing said programs;

a switching element normally having a first state for defining a first mode of operation of said computer for processing said operative programs and a second state for defining a second mode of operation for processing a debugging program for debugging said operative programs, said debugging program comprising a plurality of blocks;

a keyboard having a plurality of keys for entering into said first memory information relating to said operative programs during said first mode of operation;

a display unit for displaying information relating to said operative programs during said first mode of operation,

first means controlled by the switching of said switching element from said first state into said second state to interrupt said first mode of operation and to activate said second mode of operation,

second means controlled by the switching of said switching element from said first state to said second state to store the parameters needed to subsequently restart execution of said operative program from the point of interruption,

third means controlled by said switching element to enable said keyboard to enter information to be processed by said debugging program;

fourth means controlled by said switching elements to enable said display unit to display information relating to said debugging program;

fifth means controlled by said switching element during said second mode of operation to associate a group of predetermined keys of said plurality to a corresponding block of said debugging program and to cause said central unit to selectively activate each of said blocks to process information introduced from said keyboard before the actuation of one key of said group;

sixth means controlled by the switching of said switching element from said second state to said first state and responsive to said stored parameters for automatically restarting said operative program, whereby the switching between said modes of operation does not need any intervention by the operator for the correct restart of the operative program.

9. A computer according to claim 8 wherein said central unit comprises an addressing register for addressing the instructions of said operative program stored in the locations of said first memory during said first mode of operation, and wherein said fourth means are responsive to the address stored in said addressing register to enable said display unit to display said address and the information stored in the location addressed by said addressing register, whereby the display unit displays the address and the content of the location of the first memory corresponding to the instruction to be executed at the moment of the interruption caused by said switching element.

10. A computer according to claim 9, wherein said fifth means are responsive to the depression of a third key of said group for activating a third block of said debugging program, further comprising:

means controlled by the instructions of said third block for replacing in the location of said first memory addressed by said addressing register the information stored therein and displayed by said display unit with informations entered by said keyboard.

11. A computer according to claim 9 wherein said fifth means are responsive to the depression of a first key of said group for activating a corresponding first block of said debugging program, further comprising:

means controlled by the instructions of said first block for storing into said addressing register an address entered by said keyboard, said fourth means are responsive to the address stored in said addressing register to enable said display unit to display said address and the information stored in the location addressed by said addressing register.

12. A computer according to claim 11 further comprising:

means controlled by the instructions of said first block for incrementing the content of said addressing register at each successive depression of said first key, whereby the operator is allowed to inspect the content of said first memory starting upon the location identified by the content of said addressing register.

13. A computer according to claim 9 wherein said fifth means are responsive to a second key of said group for activating a corresponding second block of said debugging program, further comprising:

a program stop booking register;

first storing means controlled by the instructions of said second block for storing a condition indicating the actuation of said second key;

second storing means controlled by the instructions of said second block for storing into said program stop booking register a stop address entered by said keyboard;

sixth means operative during said first mode of operation for testing said condition;

seventh means actuated by said sixth means in presence of said condition for comparing the contents of said addressing register and said program stop booking register;

eighth means controlled by said seventh means in presence of the equality of said addresses for interrupting the execution of said operative program and conditioning said fourth means to display the booked address and the relevant content of the first memory.

14. An electronic computer with equipment for debugging operative programs comprising:

memory for storing instructions and data of said operative programs;

said memory including a service register for storing data not relevant at the end of each instruction;

a central unit for processing said programs;

a switching element normally having a first state for defining a first mode of operation of said computer for processing said operative programs and a second state for defining a second mode of operation for processing a debugging program for debugging said operative programs;

a keyboard having a plurality of keys for entering into said memory information relating to said operative programs during said first mode of operation,

a peripheral unit for entering information recorded in an external support into said memory;

first means controlled by the switching of said switching element from said first state into said second state to interrupt said first mode of operation and to activate said second mode of operation;

second means responsive to said switching element and controlled by a predetermined key of said keyboard for causing said central unit during said second mode of operation to transfer the program read on said support into said service register and for activating the execution of the program stored in said service register;

third means responsive to predetermined instructions of said program stored on said support for defining the starting point of the program to be executed at the end of the execution of the program stored on said support.

15. An electronic computer with equipment for debugging operative programs comprising:

a memory for storing instructions and data of said operative programs, said memory including:

a zone for storing instruction data not relevant at the end of each instruction;

a central unit for processing said programs;

a switching element normally having a first state for defining a first mode of operation of said computer for processing said operative programs and a second state for defining a second mode of operation for processing a debugging program for debugging said operative programs;

a keyboard having a plurality of keys for entering into said memory information relating to said operative programs during said first mode of operation;

a display unit for displaying information relating to said operative programs during said first mode of operation;

a peripheral unit for entering information recorded on an external support into said memory;

first means controlled by the switching of said switching element from said first state into said second state to interrupt said first mode of operation and to activate said second mode of operation;

second means controlled by said switching element to enable said keyboard to enter information to be processed by said debugging program;

third means controlled by said switching element to enable said display unit to display information processed by said debugging program;

fourth means controlled by a predetermined key of said keyboard for causing said central unit during said second mode of operation to transfer the program read on said support into said zone of the memory and

fifth means for activating the execution of the program stored in said zone;

sixth means responsive to predetermined instructions of said program stored in said zone for defining the starting point of the program to be executed at the end of the execution of the program stored in said zone.

16. An electronic computer with equipment for debugging operative programs comprising:

a memory for storing instructions and data of said operative programs, said memory including a zone for storing instruction data not relevant at the end of each instruction;

a central unit for processing said programs;

a switching element for selectively defining a first mode of operation of said computer for processing said operative programs and a second mode of operation for processing a debugging program for debugging said operative programs;

said debugging program comprising a plurality of blocks;

a keyboard for entering into said memory information relating to said operative programs during said first mode of operation;

said keyboard comprising a plurality of keys;

a display unit for displaying information relating to said operative programs during said first mode of operation;

a peripheral unit for entering information recorded on an external support into said memory,

first means conrolled by said switching element to interrupt said first mode of operation and to activate said second mode of operation;

second means controlled by said switching element to enable said keyboard to enter information to be processed by said debugging program;

third means controlled by said switching element to enable said display unit to display information processed by said debugging program;

fourth means controlled by said switching element during said second mode of operation to associate a group of predetermined keys of said plurality to a corresponding block of said debugging program and to selectively activate each of said block to process information introduced from said keyboard before the actuation of one key of said group;

fifth means controlled by a key of said group for causing said central unit to transfer the program read on said support into said zone memory and to activate the program stored in said zone.

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

The present invention relates to an electronic computer with equipment for debugging of the operative programs compiled by the operator before they are used.

Normally, in processors of high computing and storage capacity there are test or debugging programs already compiled and adapted to provide the operator with all the facilities which will enable him to follow the working out of the program under test and to obtain a visual display of any errors there may be.

It is obvious that since these debugging programs act on the programs being tested they must exist side by side with the latter in the memory of the processor. For this reason only processors of large dimensions offer these facilities.

Moreover, in the case of processors of small dimensions, the capacity of the memory is dimensioned to contain the program of maximum size from among those appertaining to the specific application of the processor (for example, application to accounting problems). Thus it is not possible for the programmer to test the compiled program, there being no available memory space. In fact, the makers of such processors tend to supply the necessary programs to the user already perfected or debugged.

This tendency finds its justification in the fact that an enlargement of the memory for the purpose of accomodating the debugging programs would affect the cost of the processor in a negative manner. Moreover, the user would acquire a processor with a low efficiency because of the unutilized portion of the memory.

The obvious disadvantage for the user deriving from this tendency is the absolute lack of flexibility of the processor purchased, inasmuch as the user is unable to personally make the slightest modification in the programs supplied with the processor.

This rigidity of performance of the processor puts the user in the position of depending entirely on the supplier of the processor for any development of service linked to a change of program.

Consequently, the user is compelled to request the supplier to modify the programs, a matter which involves long waiting times and high costs. In order to obviate these disadvantages, the user is prompted to modify the programs by himself and to ask outside computing centers for debugging of the modifications made. Even in this case, the user is forced to endure long waiting times and incur additional costs.

It is known however a minicomputer having an apparatus for debugging operative programs. This apparatus comprises a debugging panel not operable by the operator but only by the programmer. This panel includes a switch for switching the operation of the minicomputer from the normal mode to the debugging mode. There are provided also a group of switches each associated to a particular debugging operation, as displaying work memory register writing into the memory, step-by-step resuming etc.

In addition to this panel there is another panel for entering data and addresses into the memory which include also a display for displaying only two memory 8-bit bytes on binary code.

This debugging apparatus basically has two disadvantages, the first of which is of requiring specific devices and only in debugging mode and not used during the normal mode.

Such specific devices increase the cost of the debugging apparatus which therefore is expensive. The second disadvantage of such apparatus is of having a display which displays only two bytes at time.

Whereby it is difficult for the programmer to have a complete displaying of the desired memory register.

In consideration of the fact that the two modes of operations normal and debugging are mutually exclusive, there is therefore the technical problem of having a debugging equipment which utilizes the input-output devices as the keyboard, the console, the display and M.C. reader which normally equip the computer.

SUMMARY OF THE INVENTION

The main object is to carry out all the operations relating to the debugging using only the keyboard, the console and the display with which the processor is normally equipped, without making use of normally required equipment for debugging as performed in large processors.

Another object is to provide this debugging system without increasing the capacity and, therefore, the cost of the memory of the processor.

A further object is to provide a basic set of debugging programs resident in the read-only memory (ROM) of the processor and the possibility of introducing debugging programs which are pre-recorded on a magnetic card into a particular zone of the working memory (RAM) without altering the significant parameters of the programs being tested.

A further object is to enable the programmer to write and use the debugging programs most suited to his particular problem by recording such programs on magnetic cards.

BRIEF DESCRIPTION OF THE DRAWINGS

These characteristics and other characteristics of the invention will become clearer from the description and the accompanying drawings, in which:

FIG. 1a is a block diagram of the processor using the program debugging system according to the invention;

FIG. 1b is a perspective view of the processor;

FIGS. 2a, 2b, 2c show a detailed block diagram of the central unit of the processor;

FIG. 2 shows the arrangement of FIGS. 2a to 2c;

FIG. 3 shows timing signals of the central unit;

FIG. 4 shows the state register SO;

FIG. 5 shows timing signals of the state register SO;

FIG. 6 shows signals operating on the register SO during the reading of a microinstruction;

FIG. 7 shows the operative registers 30;

FIG. 8 is a block diagram of the registers 30;

FIG. 9 is a diagram of the reserved zone (ZRM) of the RAM 1;

FIG. 9a represents the program conditions byte;

FIG. 9b represents the interrupt code byte;

FIG. 9c represents the interrupt reservation byte;

FIG. 9d represents the debugging service byte;

FIGS. 10a, 10b and 10c show the flow chart of the interpreter microprogram;

FIG. 10d shows the formats of the instructions;

FIGS. 11a to 11g show the flow charts of the DBG (debugging) program;

FIGS. 12a to 12f show an example of visual display of an instruction;

FIG. 13 shows the flow chart of the bar identification microprogram;

FIG. 14 shows the summary flow chart of the operations of the debugging system according to the invention.

SUBJECT INDEX

__________________________________________________________________________ LIST OF ABBREVIATIONS Page 6 GENERAL DESCRIPTION Page 7 CENTRAL UNIT (FIG. 2) Page 9 1. Timer 20 Page 10 2. Execution of microinstructions (TABLE A) Page 11 3. State register (SO) 27 Page 17 4. Instruction register (RO) 26 Page 19 5. Operative registers 30 (scratch pad) Page 19 6. Arithmetic unit 35 Page 20 7. Switching elements 40 Page 22 8. Shift network 41 Page 23 9. Input network to the operative registers Page 24 10. Network providing connection to the RAM 1 Page 24 11. Channel logic 45 Page 27 DETAILED DESCRIPTION OF THE RAM 1 AND THE ROM 2 Page 28 INSTRUCTION INTERPRETING MICROPROGRAM Page 41 DBG PROGRAMS Page 56 1. Instructions used Page 56 2. Visual display of the instruction in the registers 362 and Page 61 3. Bar recognition Page 76 4. Program for introduction from magnetic card (Bar S2) Page 85 5. Read-RAM program (Bar S0) Page 92 6. STOP reservation program (Bar S1) Page 94 7. Writing-in-RAM program (Bar S6) Page 95 8. Step-by-step execution program (RUN key) page 96 CONCLUDING REMARKS AND EXAMPLES Page 98 CLAIMS Page 104 __________________________________________________________________________

LIST OF ABBREVIATIONS

Di = register 40, indicates the eight switching elements

Dev = a switching element of the register 40, specified by three bits

Crt = character, corresponds to eight memory bits

Mem = memory RAM 1

Ind = address

Mls = sequence logic matrix 28

Rb = base register

P1 = pointer 1

P2 = pointer 2

Cp = program conditions

Ci = interrupt code

Mi = instruction modification

Dbg = debugging

Bsd = dbg service byte

M.c. = magnetic card

Exor = exclusive-OR

Ci = interrupt code

Ip = program addresser (207)

Ai = enable interrupt

Psr = program in progress (Register 300 of RAM 1)

Ipsr = interrupt program (Register 302 of RAM 1)

Opsr = interrupted program (Register 301 of RAM 1)

Zrm = reserver zone of RAM 1

Rc = current reference

Cc = condition code

Cu = central unit 3

Pu = peripheral unit 4

Ir = reentry address (Reg. 327, FIG. 9)

Ii = addresses of interrupt program (Register 335 of FIG. 9)

Is = stop address (Register 350, FIG. 9)

Bsd = debugging service byte (Register 351 of FIG. 9)

Rl = working register (Register 352 of FIG. 9)

Ab = enable bars

Itr = reference Table address register.

DESCRIPTION OF PREFERRED EMBODIMENTS

A brief description of the processor using the program debugging system according to the invention will now be given with reference to FIGS. 1a and 1b.

Of course, reference is made herein to a particular embodiment of the processor without on that account limiting the possibilities of application of the system according to the invention to other types of processor.

More particularly, the processor of FIGS. 1a and 1b is of the microprogrammed type. That is, to each instruction of the program there corresponds a microprogram recorded in a permanent memory. The execution of a program instruction is achieved by means of the sequential execution of the microinstructions of the respective microprogram.

The processor of FIGS. 1a and 1b comprises a memory RAM 1 adapted to contain the instructions and the data of the program in process of execution, and a memory ROM 2 adapted to contain both the microprograms which implement the instructions of the programs and the programs used by the debugging system according to the invention, as will be better explained hereinafter.

The RAM 1 and the ROM 2 may be of any known type on the market and will therefore not be described in detail; it is only made clear that each cell of both of the memories is adapted to contain 16 bits.

The RAM 1 and the ROM 2 are connected to a central processing unit 3, which will be described in detail hereinafter and which is connected in turn to a group of peripheral units 4.

The peripheral units 4 may be of various kinds according to the particular application for which the processor is intended. In this particular case, there will be described and demonstrated hereinafter only the peripheral units used by the debugging system according to the invention. More particularly, the peripheral units shown are: an alphanumeric keyboard 5, a visual display 6, a control console 7, a printer 8, and a read/write unit 9' adapted to record and read data on a magnetic card 9. The read/write unit 9' is of the type described in U.S. Pat. No. 3,495,222 issued on Feb. 10, 1970 and assigned to the same assignee of this application.

There will now be described briefly with reference to FIGS. 1a and 1b the operations which the programmer must carry out during the stage of debugging a program recorded previously in the RAM 1. Of course, these operations will be described in detail later on.

Let it now be assumed that the program recorded in the RAM 1 is not being executed correctly by the processor because of errors of various kinds which the programmer may have made during the compilation thereof.

At this point, the programmer intends to carry out a check of the instructions of the program which the processor is not able to execute. He presumes that one of them is wrong. To correct this instruction directly in the RAM 1, the programmer acts on the console 7, positioning a key change-over switch 100 (FIG. 1b) from the normal setting to the debugging setting, writes the respective address of the instruction on the numeric part 101 of the keyboard 5 and then actuates a service bar S1 belonging to a group of bars 102.

Corresponding to this operation, an interrupt is generated in the program to be corrected (being caused by the switch 100 actuated on the console 7) and one of the debugging programs recorded in the ROM 2 is performed, the program being associated with the particular bar actuated on the keyboard 5. This program, for example, may have the effect of producing a visual display of the instruction corresponding to the address written on the keyboard and halting of processing with enabling of the keyboard 5. In this way, the programmer can enter the instruction he considers correct on the keyboard 5. Thereafter, the operator actuates another service bar S6 with which is associated another debugging program which records the correct instruction in the memory RAM 1 at the address previously entered.

The programmer may wish to carry out a debugging program different from those recorded in the ROM 2. If so, he inserts in the reader 9' the magnetic card 9 on which the desired debugging program is recorded, and actuates the service bar S2. This bar calls a special program of the ROM 2 which causes: the reading of the program recorded on the card 9, the transfer thereof to a fixed zone (ZRM) of the RAM 1, and the immediate execution of this program.

It is emphasized -- and this is explained in detail hereinafter -- that the fixed zone of the RAM 1 to which the card program is transferred does not contain information significant for the resumption of the program under test. Thus there is no loss of information in performing the debugging program recorded on the magnetic card 9. From what has been said, one of the advantages of the system according to the invention becomes obvious, i.e., the possibility of testing programs simply by actuating a change-over switch and using the same devices (keyboard, display, magnetic card) which are used during normal operation.

CENTRAL UNIT (FIG. 2)

A detailed description of the central unit 3 will now be given with reference to FIG. 2.

The central unit 3 is an assembly of logic circuits which handle and execute the various microprograms contained in the ROM 2.

It is composed of the following main blocks:

A timer 20 which times the development of the processing of the data inside the control unit 3. This timer is composed of an oscillator 21 and an assembly of signal generating circuits 22.

A sequence logic matrix network 25, which staticizes and interprets the codes of the microinstructions read from the ROM 2 and generates the commands necessary for the execution thereof. This network is composed of a microinstruction register (R0) 26, a state register (S0) 27 and a sequence logic matrix (MLS) 28.

An operative network which carries out the processing of the data by methods imposed by the sequence logic matrix 28. The operative network comprises: the operative registers 30 (scratch pad) which are divided into two groups RA-31 and RB-32 each of which is composed of sixteen eight-bit registers hereinafter referred to as AO-A15 and BO-B15, respectively; an arithmetic unit 35 which is formed by three blocks UA-36, UB-37, UC-38 with eight-bit parallelism; the switching elements DI-40; a shift network ND-41, an input network to the operative registers which comprises the nodes NA and NB and two registers BA-42, BB-43, and a network providing connection with the RAM 1 and composed of nodes NO and NC; a channel logic 45 which controls the interface providing connection to the peripheral units and monitors the operative simultaneity of the central unit 3.

A detailed description of the above-enumerated blocks will now be given.

1. Timer 20

The oscillator 21 generates periodic pulses which define a fixed period of time called the machine cycle which lasts for the time necessary for the execution of an elementary operation (for example: reading of an operative register 30, its incrementing and rewriting in the operative register 30).

During the machine cycle, signals are generated by the circuit 22, the duration of which and the positioning of which in the machine cycle are fixed.

The function of these signals is predetermined. The fact that they act or do not act on the circuits of the central unit 3 is determined by the conditions generated by the sequence matrix 28 in the manner to be described hereinafter.

The working of the central unit 3 is completely synchronous with this timing, as is also the conversation with the peripheral units.

Ten signals are generated by the circuit 22 and their use is illustrated hereinafter. The signals are:

T0 which acts on the state register 27,

T1 which times the reading of the ROM 2,

T2 which times the RAM 1,

T3a which acts on the register R0-26,

T3n which also acts on the register R0-26,

T4a which acts on the registers BA42, BB43 and on the switching elements 40,

T5 which acts on the operative registers 31 and 32,

T6 and T7 which act on the channel logic 45.

FIG. 3 is a timing diagram in which the signals mentioned appear.

Of course, the oscillator 21 and the circuits 22 are not described in detail, since they are known in the field of circuit design.

2. EXECUTION OF MICROINSTRUCTIONS

Before proceeding to the description of the other blocks of the central unit 3, a brief mention will now be made of the microinstructions used by the central unit 3 in the debugging system according to the invention and of the execution thereof.

The execution of a microinstruction can be divided into two phases: An interpretive phase, common to all the microinstructions, which reads the address microinstruction from the ROM 2, prearranges the carrying out thereof and increments the addresser of the ROM 2. This phase is obviously independent of the code of the microinstruction read. An execute phase, during which the processing of the data takes place in accordance with the procedures indicated by the microinstruction read in the preceding interpretive phase. The interpretive phase is always performed in a single machine cycle and the configuration of the signals (hereinafter called "commands") is stable within the limits of the cycle. The configuration of these commands defines the operations to be performed and is called the "Interpretive State."

The presence of the interpretive state is indentified by a flip-flop S000 of the register 27 (FIG. 4).

The execute phase is performed in one or more machine cycles to which there correspond as many states, each defined by a corresponding flip-flop of the register 27.

Throughout the execute phase, the code of the microinstruction in question remains stable in the register 26, while the situation of the flip-flops of the register 27 which define the current state develops.

Each state defines the next as a function of the code of the microinstruction read.

At the end of the execution of each microinstruction a return is made to the interpretive state S000 to read the following microinstruction from the ROM 2.

During the two phases, the interpretive phase and the execute phase, the combinatory network 28 (MLS), which has the registers 26 and 27 as inputs, generates commands C which enable given flows of information through the operative network or the other blocks of the central unit 3.

The information then flows between the blocks of the central unit 3 through a series of AND gates of various types which are controlled by the commands C generated by the combinatory network 28. In FIG. 2 these gates are symbolically represented divided into three zones. The central zone contains the control signal of the gate generated by the network 28 (MLS). When this command is present, the signals at the input of the gate are transferred to the following block. The pairs of numbers varying from 00 to 15 which are in the top zone and the bottom zone of the gates indicate the number of bits which they allow to pass and more precisely the positions in which these bits are at the input and the output. For example, a gate having the pairs of numbers 07, 00 both input and output is a gate which transfers an eight-bit character in direct parallel. On the other hand, a gate having the pair of numbers 03, 00 in the top zone, that is as input, and the pair of numbers 07, 04 in the bottom zone, that is as output, is a gate which transfers four bits shifting them to the left by four places. If 07, 04 are input and 03, 00 are output, the shifting is by four places to the right. Finally, if the input zone is empty, this signifies that the bits are forced into the gate from outside.

There is described hereinafter, with reference to Table A, the set of microinstructions used by the debugging system according to the invention, omitting the other microinstructions which the central unit is capable of carrying into effect. The microinstructions given in Table A have a fixed format of sixteen bits which corresponds to one word of the ROM 2. The format of the microinstructions is as follows: ##SPC1##

The fields, each of four bits, have the following significance:

F is the operative code of the microinstruction;

X indicates the first operand;

Y indicates the second operand;

Z is an extender of one of the foregoing fields.

When the fields X and Y specify as operands the registers A, B or L of the operative registers 30, they will be indicated in the microinstructions by the symbols Ax, Bx, Lx, Ay, By, Ly, respectively.

The microinstructions are divided into groups distinguished by the different function code, that is by the different binary configuration of the field F of the microinstruction.

The microinstructions having the same function code are executed with the same sequence of states.

TABLE A __________________________________________________________________________ Name F X Y Z FUNCTION __________________________________________________________________________ LOGICAL ARITHMETIC ADDB 0110 A B 0101 B.rarw. (A+B) ANDA 0110 A B 1000 If (A.rarw.A AND B) = 0 ANDB 0110 A B 0100 If (B.rarw.A AND B) = 0 PUTS AND 0110 A B 0000 if (A AND B) = 0 ORA 0110 A B 1110 If (A.rarw.A OR B) = 0 ORE 0110 A B 0111 If (A EX OR B) = 0 SOT 0110 A B 0010 If (A - B)>0 D00 = 1 TRANSFER TAB 0101 A B 1100 B.rarw.A TBA 0101 A B 0011 A.rarw.B EXCHANGE SLL 0100 L L 1111 Ax.revreaction.By; Bx.revreaction.Ay DECREMENT DCA 1010 A 0100 1010 If (A.rarw.A - 1) = 0 puts D01=1 LOAD SWITCHING ELEMENT TAD1 1011 A 1110 0111 DI.rarw.A TBDI 1011 B 1111 0111 DI B REDI