 |
Description  |
|
|
BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of this invention includes digital circuitry for synthesizing an
analog waveform of a particular desired shape.
The primary application of this invention is in a communication system for
digital data and particularly involves such communication systems as are
adapted for connection to telephone lines, associated telephone circuitry
and the like. More particularly, the transmitter of this invention is
substantially entirely digital and, thus, is readily subject to an
integrated circuit manufacturing technique.
2. Description of the Prior Art
The concept of providing a modem adaptable for integrated circuit
manufacturing is a familiar desire known to the prior art. For example,
such a modem is discussed in an article entitled: "The Use of Digital
Circuit in Data Transmission," Philips Technical Review, Vol. 30, No. 3,
Pages 71-81, 1969. In that article the stated goal was to design an all
digital transmitter as an integrated circuit, wherein, digital signals are
modulated onto a carrier and the signal is filtered by a digital
transversal filter. As is typical in such prior art techniques broad
bandwidth is employed in order to maintain signal integrity over the
entire modulation period. This means that the entire frequency spectrum of
the communication link, such as a telephone line, is utilized in order to
transmit the digital modulated signal from one modem transmitter to one
modem receiver. A great deal of bandwidth is thus wasted. In addition, the
modem there described utilizes a complex and sensitive digital transversal
filter. This component includes numerous weighted resistors that must have
extremely precise values. Such resistors are not readily subject to an
integrated circuit manufacturing technique. Furthermore, the complexity of
operation of this prior art modem transmitter is a limiting factor in its
feasibility and commercialization.
In U.S. Pat. No. 3,524,023, issued Aug. 11, 1970, by Sang Y. Whang, and
assigned to the same assignee as the present invention, a narrow bandwidth
modem utilizing a single carrier/double sideband is described and claimed.
Each serial group of digital signals to be transmitted during each given
modulation interval are passed through a bandpass filter which has a
bandpass of 1/T Hz with its center frequency of f.sub.o, the carrier
frequency. The phase characteristic of the filter and its associated
communication link is substantially linear within the narrow passband and
a highly unusual wave shape is developed. Reference to the above-mentioned
patent will supply details of operation if desired. Briefly, however,
certain fundamental concepts of the above-mentioned patent will be
described to enhance a clearer understanding of this invention. As
discussed in the above-mentioned patent, extremely narrow bandwidth is
utilized for data transmission regardless of the type of modulation
utilized. As typical examples, the carrier frequency, f.sub.o, may
conveniently be located between 1600 and 1800 Hz for transmission of
either 2400 bits per second or 4800 bits per second. Bandwidth based upon
groups of three serial bits in a differential phase modulation system is
about 800 Hz for 2400 bits per second or is about 1600 Hz for 4800 bits
per second. The passband for the two typical examples given is, thus,
approximately 1300 Hz to 2100 Hz for 2400 bits per second or 900 Hz to
2500 Hz for 4800 bits per second, with f.sub.o located at 1700 Hz.
In U.S. Pat. No. 3,128,343, issued Apr. 7, 1964, to P. A. Baker, another
prior art data communication system is disclosed. In the Baker system
incoming digital data is grouped into bit pairs called dibits. Two
separate channels are employed in the transmitter with each channel
alternately encoding successive dibits as differential phase angles in a
carrier signal. A raised cosine impulse response is amplitude modulated on
the carrier in each channel. The raised cosine impulse response, at one
half the transmission rate, is switched from one channel to the next in
the channel pair so that the differential phases in the channels do not
significantly interfere with one another. The signals from both channels
are applied to a telephone line. The various circuits employed in the
Baker patent are analog rather than digital in nature. There is no
suggestion that any particular signal spectrum be digitized as a plurality
of discrete values that are stored in a memory. Mentioning such patent, as
prior art with respect to applicant's invention, is simply based upon the
fact that a data modulated carrier may be alternated as a pair of signals,
with one signal each for one channel each for a pair of channels.
SUMMARY OF THE INVENTION
Our invention in its broadest aspect comprises a transmitter in which a
carrier signal is modulated by digital data to be transmitted over a
communication link, wherein the data modulated carrier is represented by a
unique group of discrete signal values stored in a memory. The memory,
upon command, reads out a predetermined sequence which represents the
signal shape of a digital data modulated carrier. The predetermined shape
appears as though it had been passed through a narrow band limited linear
phase network having a passband width of 1/T Hz with a center frequency of
f.sub.o, where f.sub.o is the carrier frequency in cycles per second.
In one preferred embodiment of our invention, the predetermined signal
shape occupies a signal spectrum which extends in time for a frame, with a
frame comprising four successive modulation periods. In this particular
embodiment, four successive frames are utilized to form a composite
signal. Each frame's starting point in time is offset by one modulation
period with respect to the preceding frame. The memory storage device of
our transmitter, upon command, reads out several discrete sequences. A
summing circuit is connected to the output of the memory storage device
and is timed in such a manner that it collates the sequence of signals as
they are read from the memory. The summing operation generates in a
digital manner a composite data modulated carrier for application to a
communication link.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the transmitter of our invention;
FIG. 1A is an illustration of waveforms from the aforementioned prior art
patent;
FIG. 2 is an illustration of waveforms useful in explaining certain of the
operational concepts of the transmitter of FIG. 1;
FIG. 3 is a more detailed block diagram of a selected portion of the
transmitter of FIG. 1;
FIG. 4A is a timing chart useful in describing the operation of the
circuitry of FIG. 3;
FIG. 4B depicts waveforms useful in describing the timing operation of FIG.
3;
FIG. 5 is a more detailed block diagram of another selected portion of the
transmitter of FIG. 1; and
FIG. 6 depicts digital to analog circuits adapted for connection to the
output leads depicted in FIG. 5;
FIG. 7 is a signal chart useful in explaining the operation of the
apparatus of FIG. 6.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 discloses a block diagram of a digital transmitter 100 in accordance
with the principles of this invention. As earlier stated the ultimate goal
of this invention is to provide a modem transmitter which may be readily
and economically manufactured as an integraed circuit. In this regard it
is believed helpful to generally summarize the operation of the
transmitter 100, FIG. 1, before setting forth a more detailed description
of our invention.
In its broadest concept the transmitter 100, FIG. 1, comprises an input
circuit 20 for receiving serial data along with an input circuit 21 for
receiving a clock signal as is normally the case in all data modem
transmitters. This invention may employ frequency modulation, phase
modulation, amplitude modulation, or any combination of same.
Simply for ease of description a preferred inventive embodiment employing
differential phase modulation will be described in connection with the
block diagram transmitter 100, FIG. 1. As is well known, in differential
phase modulation phase shifts in a selected carrier are assigned from one
modulation period to the next. The difference between the phase in two
adjacent modulation periods, identifies the data represented in a given
modulation period relative to the data represented in a previous
modulation period. In the particular transmitter of this invention, a pair
of memories are employed in the transmitter. Such memories may be of the
read only memory type as they are particularly well suited for integrated
circuit manufacturing techniques. Obivously, however, other memory types
suitable for integrated circuit manufacturing techniques may also be
employed.
Assume, for example, that the incoming binary data is grouped into any
convenient multi-bit grouping. Each multi-bit grouping is applied to a
first read only memory (hereinafter ROM) which is located in the binary
data to phase change encoder 25. Encoder 25 emits timed digital outputs
which are representative of differential phase amounts. These differential
phases are assigned, in any selected manner, a given amount which
identifies the unique bits present in the multi-bit groupings. The digital
output signals from encoder 25, timed by address counter 10, constitute
one portion of an address signal that is received by a memory address
circuit 30. Address circuit 30 subsequently applies these digital outputs
to a digital storage memory 50. Address counter 10 provides another input
signal to the memory addressing circuit 30. These two signals, namely an
output signal from encoder 25, and an output signal from address counter
10 are utilized by memory addressing circuit 30 to fully address digital
storage memory 50.
Memory 50 is addressed in such a manner that predetermined relative phase
changes in a selected carrier signal are emitted as a predetermined
sequence of unique digital characters. These unique digital characters
will be more fully described hereinafter with respect to FIG. 5. Briefly,
however, memory 50 stores a large number of discrete unique constants in
the form of encoded digital words. Upon command from memory addressing
circuit 30 and address counter 10, the encoded digital words are read in a
given timing sequence from memory 50. Each sequence extends over several
modulation periods in order to fully define each given absolute phase
amount. A summing circuit 60, also timed by the transmitter timing control
40, collates or sums the binary bits of the encoded words as they are read
from memory 50. The summed signal from circuit 60 is applied to a digital
to analog converter 70. The converter 70, in response to a summed signal
from circuit 60, forms a composite differential phase waveform for
application to a communication link. Experience has shown that the
composite line signal of this invention is optimum for application over
various classes of telephone lines including those poor quality telephone
lines which exhibit irregular and erratic amplitude and delay
characteristics.
With the general description in mind, reference is now made to FIG. 1A
which depicts certain waveforms presented in the Narrow Band Limited
Telephone Line Data Communication System, U.S. Pat. No. 3,524,023 assigned
to the present assignee.
FIG. 1A depicts a step function input 110 for an entire modulation period
T. If such an input is applied to a linear phase 1/T Hz bandpass filter of
the narrow characteristics described in the abovementioned patent, then
the filter's output is one-half of the envelope 111 shown in dashed lines.
If, on the other hand, a sine wave input 113, is applied as an input
signal to the narrow bandpass filter, the filter's output is a full
envelope having the analog signal 112 present with diminished amplitude
ringing into several adjacent modulation periods.
As described and claimed in the aforementioned patent, the narrow
bandlimiting filter preserves the integrity of the transmitted phase of
the input carrier signal 113, in the middle of the modulation period.
Other portions of signal 112 do not maintain phase integrity and are
useless for data sampling. The unique signals are readily available for
derived clock timing, ease of equalization and other advantages as
described in the aforementioned patent. The present invention makes use of
the discoveries of the aforementioned patent and improves upon that
patented invention.
FIG. 2, Line A depicts a typical carrier which may be 1800 Hz associated
with a modulation period of 1/1200 seconds. Any suitable carrier frequency
may be employed in this invention, and the description and claims are not
to be limited by the specific examples discussed herein. As shown in FIG.
2 the carrier signal 213 has 11/2 cycles present in a given modulation
period T.
The principles of a preferred embodiment of our invention will be explained
with reference to a signal spectrum of four sectors per frame. Our
invention is not limited to four sectors only. Those skilled in the art
will recognize that more than four sectors could be employed since the
number of sectors is a function of the available bandwidth and the bit
rate being transmitted.
Carrier 213, during modulation period T.sub.o, is arbitrarily assigned an
absolute phase angle corresponding to 0.degree.. By absolute it is meant
that carrier 213 alone, i.e., with several modulation periods on every
side of 213 being free of any signals, is passed through the
aforementioned narrow passband filter of 1/T Hz. In such a situation it
was discovered that the filtered signal rang for several modulation
periods. In our invention we forced the signal shape to ring quickly to a
neglible value while still maintaining phase integrity at the middle of
the signal's spectrum. For example, it was discovered that four sectors,
or modulation periods, was a convenient and satisfactory number for most
modem transmitting speeds.
The generalized mathematical expression of the spectrum I.sub.(t), of a
single given input signal, such as signal 213 is defined as follows:
I.sub.(t) = [pulse response] [amplitude] [sine.omega.t+ .theta.]
Where: a. The pulse response of a step function input (such as 110, FIG.
1A) as subjected to a 1/T Hz narrow bandwidth filter;
b. The amplitude is any selected amplitude and need not be fixed as will be
explained later;
c. .omega. is related to the carrier frequency f.sub.o, which in our
exemplitive case is 1800 Hz; and
d. .theta. is any selected angle, which in our exemplitive case will be (2N
.times. 45.degree.), where N is 0, 1, 2 or 3.
The analog shape of different absolute phase angle amounts (assuming a data
modulated carrier 213) have different signal spectrums over their own four
sectors. Thus at lines B, C, D and E of FIG. 2 signal spectrums for
absolute phase angles of 0.degree., 90.degree., 270.degree., and
180.degree., respectively, are depicted. The composite waveform shown in
Line "F" of FIG. 2 is ultimately presented as an output from transmitter
100 to the telephone line over which the modem transmitter is to operate.
Reference is now made to FIG. 3 wherein the encoder 25 of FIG. 1 is shown
in more detail. Encoder 25 includes a first ROM 325, whih responds to the
clock signal output from a divide-by-two circuit 326 to read out any
preselected digital character. As a typical example, ROM 325 may operate
in any one of four possible modes which will be more fully described
hereinafter. The particular mode depicted for ROM 325 in FIG. 3 is mode
"A." Four possible binary pair input conditions to ROM 325 are 00, 01, 10,
11. Associated with each possible input bit pair at the output of ROM 325
in mode "A" is a digital output character indicative of phase angles of
90.degree. multiples. In mode "A" the digital characters from ROM 325
comprise three bits per character. In the exemplitive character of mode
"A" the least significant bit is at the right hand side. A binary "one" in
that position corresponds to a 45.degree. angle, (in mode "A" there are
none). The most significant bit is on the left hand side and a binary
"one" in that position corresponds to a 180.degree. angle. A binary "one"
in the middle bit position corresponds to a 90.degree. angle.
It is essential that the inherent 180.degree. phase difference due to the
11/2 cycles of carrier 213 be adjusted for by encoder 25. Without
considering any data modulation whatsoever, carrier 213 changes phase by
180.degree. in each adjacent modulation period. As depicted earlier at
line A, FIG. 2, as previously described, carrier 213 is shown in solid
line (modulation period) T.sub.o) and in dashed lines (modulation period
T.sub.1) as it would normally appear. Obviously carrier 213 is out of
phase by 180.degree. when the signal present in T.sub.1 is compared with
the signal present in T.sub.o. If 180.degree. is added to carrier 213
during each modulation period T, then carrier 213 in adjacent modulation
periods T.sub.o and T.sub.1, etc., is always in phase. Stated another way,
the carrier signal present during each modulation period, without
data-representing phase changes involved, will exhibit a 0.degree. phase
shift when 180.degree. is added in each modulation period, T.
The 180.degree. phase change is accomplished in ROM 325, FIG. 3, as shown
by adding 180.degree. for the input bit pair 00. As earlier described the
output character 100 with a "one" in the left hand position adds
180.degree. and this compensates for the inherent phase shift in carrier
213. Thus, ROM 325 for input pair 00 emits an in-phase signal, or
0.degree. differential phase, output value of carrier 213.
The four possible binary input bit pairs described earlier are depicted,
from top to bottom in the input column of ROM 325, as they might appear in
time during a random string of input data. The .DELTA. .theta. or required
angle change assigned to each binary bit pair combination is shown in the
second column of ROM 325. This .DELTA. .theta. is the angle that is
desired for ultimate application to the telephone line. In the third
column of ROM 325, 180.degree. is added to correct for the inherent phase
shift of carrier 213 as described earlier. The last column of ROM 325
depicts the actual binary characters respectively read out from ROM 325.
Output characters from ROM 325 are applied to binary adder 327 which may be
any conventional binary adder. It is assumed simply for a starting
condition that an initial character "I" is stored in the binary adder.
Thus, at starting time t.sub.o, character "000" is shown in the top, or
output portion, of adder 327.
This first character "I" ("000") is applied to the memory address circuit
30 by binary adder 327 in the manner depicted in FIG. 4.
Reference to the waveform and timing diagram of FIG. 4A at row A, shows
that a ready to send signal (RTS) was true or high, during this start
period. The true condition and the initial character I ("000") being
present in the top position of binary adder 327, FIG. 3, are proper
conditions to start the transmitter operation. At time t.sub.o, character
"I" is applied as .theta..sub.n to memory address circuit 30. The data, at
Row B of FIG. 4A, follows this arbitrarily assumed input condition. The
next exemplitive bit pairs, in the order received are 01, 00, 10 and 11.
These bit pairs are serially loaded into the input exchange of ROM 325 by
the 2400 Hz data clock. This data clock is divided down to the baud rate
of 1200 bits per second by circuit 326, FIG. 3. The output of divider 326
reads out the characters from ROM 325, which characters are representative
of the change in phase plus 180.degree..
Adder 327 receives the characters from the output of ROM 325. Adder 327,
supplies binary characters to accumulator circuit 340, which operates in
response to the baud rate clock from divider 326. Adder 327 and
accumulator 340 cooperate to accumulate successive characters after they
are read from ROM 325 and binarily add each character, stored in binary
adder 327, to a previous character, .theta.n-1, as supplied by accumulator
340.
The binary accumulator circuit 340 may be any conventional accumulator
circuit as is well known in the prior art. Its operation will now be
described with reference to the initial starting condition, namely, that
character I ("000") at time t.sub.o is present in the top position of
adder 327. This initial character I in this case is assumed to represent a
data-modulated angle of 0.degree. in carrier 213. Output .theta.n at time
t.sub.o FIG. 4A, is sent to memory address circuit 30. The next data bit
pair "01" is thereafter input into ROM 325. At time t.sub.1, FIG. 4A, an
output character A ("010") is read from ROM 325 under control of the read
ROM signal from divider 326. This output character A ("010") is supplied
to the binary adder 327 and it is added to the previous character I,
("000"). The resultant binarily added signal total is "010." . The
character "010" represents a data-modulted differential phase shift of
90.degree. to carrier 213. The resultant "010" then assumes the top
position in binary adder 326 in the manner just described. Reference to
FIG. 4A shows that this character A is supplied to memory address circuit
30 as .theta.n+1 at time t.sub.1. The binary accumulator 340 repeats the
operation just described when the next character B ("100") is read from
ROM 325 shortly fter time t.sub.1. Thereafter the operation continues in
the manner described such that bit pairs 10, 11, 01, etc., are represented
by characters C, D, E and the like.
It should be noted, in the operation of the transmitter 100, FIG. 3, as
described thus far, that differential phase angle represented by binary
encoded words are emitted to memory address circuits 30 by binary adder
327. Thus the binary words representing characters "I" "A" "B" and "C"
(FIG. 4A) each differ from the preceding character encoded word by a given
angle that represents the data. It should be understood, also that as
described thus far provision has already been made to adjust for the fact
that the original 1800 Hz carrier always includes 11/2 cycles per
modulation period. If some other carrier signal were selected, then a
similar adjustment could be made for the expected repetitive phase
difference of the selected carrier per each modulation period. For
example, if a carrier of 1200 Hz were selected for a slower transmission
rate, then it is obvious that no phase correction need be added because
there is no phase difference from one modulation period to the next. FIG.
4B as will be more fully explained hereinafter represents the analog forms
of the differential phase angles represented by the binary words from the
phase change encoder 25.
FIG. 5 depicts additional details of memory addressing circuit 30 and
certain other block diagrams of the transmitter 100 of FIG. 1. Binary
adder 327 supplies the relative phase angles (previously discussed) to
memory address circuit 30 which includes a shift register 510. Shift
register 510 may be any suitable shift register of a well known type
suitable for integrated circuit manufacturing techniques. The particular
example utilized in the exemplitive description of our invention is a four
by four shift register with the least significant and most significant
bits of the characters from adder 327 occupying the positions shown on the
inputs to memory address circuit 30. Shift register 510 also receives from
address counter 10, FIG. 1, shift pulses which are four times as fast as
the counting rate for reading out constants from the data constant memory
50. This counting rate will be described in greater detail hereinafter.
The top row of shift register 510 normally contains binary zeros except
when a soft carrier signal (SCS) is present. Zeros present in the top row
of register 510 inhibit reading of any data from ROM 50 via an inhibit
signal applied to ROM 50 by lead 511 in a manner well known for read only
memories. An SCS condition on the other hand is represented by a binary
"ONE" present in the top output stage of shift register 510. When the
ready to send level is true, and SCS is present, it is indictive of a data
constant request for ROM 50. Simultaneously, of course, the inhibit signal
which prevented reading out values from ROM 50 is removed.
The soft carrier control (SCS) signal is depicted true in FIG. 2 for four
different phases only that go over the the telephone line, Row F, FIG. 2,
to build up gradually and decay gradually in the manner shown. It should
be understood, of course, that many data bits would be transmitted before
SCS goes false, and thus FIG. 2 is diagrammatic only. In any event,
however, SCS signal goes true at the very beginning of the first signal
sector and it persists true until the very last sector of the last signal
frame that is transmitted. Because the beginning and end of the sectors
commence and diminish in amplitude, low-valued constants are read from ROM
50. It is apparent that during these periods ROM 50 is alternately read
and inhibited during the first sector of the first frame such that
constants for the first sector of 0.degree. phase only are provided from
ROM 50. A similar sequence, of course, takes place at the termination of
data transmission.
To appreciate in detail, how discrete constants are read out from ROM 50,
reference is made to FIG. 4B and the four sectors in the first frame
assigned to the initial character "I." The signal depicted during this
first frame represents a 0.degree. phase angle for the telephone line
signal as discussed hereinbefore. Comparison of the wave form of character
I with other characters shown in FIG. 4B discloses that during sector 1,
only constants indicative of the amplitude for 0.degree. phase are
present. During this sector 1 for character I (hereinafter sector I.sub.1)
the other characters are not yet present because each character's frame is
offset by one sector, or modulation period, from the start of preceding
character's frame.
Any convenient number of read commands may be applied to ROM 50 during a
given frame. The number of signals, N, present during a frame is strictly
a function of how many samples are sufficient to reconstruct the desired
analog signal via a desired number of unique digital constants in one
frame. Assume that N is equal to 48 samples per frame, as a preferred
number for this embodiment. Character I is a 0.degree. waveform which is
thus made of 12 unique constants in each one of its four sectors I.sub.1,
I.sub.2, I.sub.3, and I.sub.4.
The 48 constants for a 0.degree. phase angle is shown in decimal form in
Table 1. Approximate values rounded off to the third decimal position are
given in Table 1. It is not necessary to give the decimal value for every
angle because they can readily be determined by those skilled in the art
by simply
TABLE 1
______________________________________
FRAME 1 DECIMAL VALUE ADDRESS COUNTER
______________________________________
0 N + 1
0.016 N + 2
0.016 N + 3
0 N + 4
0 N + 5
0.016 N + 6
SECTOR 0.031 N + 7
I.sub.1 0 N + 8
-0.063 N + 9
-0.109 N + 10
-0.078 N + 11
0 N + 12
0 N + 13
-0.125
-0.188
0
0.484
SECTOR 0.922
I.sub.2 0.813
0
-1.125
-1.734
-1.297
0 N + 24
1.300 N + 25
1.734
1.125
0
-0.813
SECTOR -0.922
I.sub.3 -0.484
0
0.188
0.125
0
0 N + 36
.078 N + 37
.109
.063
.0
-.031
SECTOR -.016
I.sub.4 0
0
-.016
-.016
0 N + 48
0
______________________________________
measuring the amplitude value of an angle-modulated carrier passed through
the 1/T Hz narrow band filter to derive similar amplitude tables for all
other angles as desired.
Although the amplitude values of Table 1 are shown as decimal amounts, for
ease of understanding, it is to be understood that they are actually
represented in ROM 50 as binary words for each discrete decimal value. The
binary words, for example, may be expressed as an 8 bit binary word. The
manner in which these binary words are read out in a timing sequence will
now be explained by reference to Table 2 taken in conjunction with FIG. 5
and the waveforms of FIGS. 4A and 4B.
TABLE NO. 2
__________________________________________________________________________
FRAMES 1 & 5 FRAMES 2 & 6 FRAMES 3 & 7 FRAMES 4 & 8
(CHARACTERS I & D)
(CHARACTERS A & E)
(CHARACTERS B & X)
(CHARACTERS A & Y)
(FIGS. 4A & 4B)
(FIGS. 4A & 4B)
(FIGS. 4A & 4B)
(FIGS. 4A & 4B)
__________________________________________________________________________
N + 1
Sector
1 0.degree.
N + 12
N + 13 M + 1
Sector
2 0.degree.
Sector
1 90.degree.
N + 24 M + 12
N + 25 M + 13 O + 1
Sector
3 0.degree.
Sector
2 90.degree.
Sector
1 270.degree.
Sa-1.fwdarw.
N + 36 M + 24 O + 12
Sa.fwdarw.
N + 37 M + 25 O + 13 P + 1
Sector
4 0.degree.
Sector
3 90.degree.
Sector
2 270.degree.
Sector
1 0.degree.
N + 48 M + 36 O + 24 P + 12
Q + 1 M + 37 O + 25 P + 13
Sector
1 180.degree.
Sector
4 90.degree.
Sector
3 270.degree.
Sector
2 0.degree.
Q + 12 M + 48 O + 36 P + 24
Q + 13 R + 1 O + 37 P + 25
Sector
| | |
