A general purpose logic chip may be replicated for use to construct both the arithmetic unit and the control sections of a computer or other digital data processing or logic circuitry. The chip includes a number of features which when taken together permits its use for a wide variety of data processing functions, including as noted above, the basic arithmetic logic unit and associated functions in addition to micro-operational code control functions. The chip includes a 4-bit arithmetic unit and four registers associated with the arithmetic unit for handling inputs or outputs to and from the arithmetic logic unit. Mode code terminals are provided to implement micro-program control logic circuitry permitting several of the chips to operate on "bytes" or sets of bits of long digital numbers in parallel, without additional circuitry. A random access memory having 16 words, 4 bits each, is provided with alternative addressing circuits to be conveniently accessed either as a "first-in, last-out stack" or as a random access memory register file, or both. Required timing and control are developed within the chip and associated memories to minimize the need for special or additional control circuitry. Additional flexibility is provided for multiple multiplexing circuitry and circuit implementation permitting direct connection of leads from several of the chip outputs. A number of chips of this single type of chip are employed in the implementation of a large class of computer and other data processing systems, employing input/output functions, memory process functions, as well as arithmetic and central processing unit functions.
A versatile programmable multi-bit shifter is provided which can be built on a single monolithic integrated circuit. The shifter is capable of performing arithmetic shift left, arithmetic shift right, rotate left, rotate right, shifting right using two's complement, shifting left using two's complement, forcing the output to a predetermined logic level, or placing a sign bit at all the outputs. The programmable multi-bit shifter comprises an input data multiplexer for receiving input data and an output multiplexer coupled to the input multiplexer. The output multiplexer provides the data output for the shifter. A decoder is also provided for decoding shift function inputs. A second decoder is provided for decoding scale factor shift inputs. Outputs of the second decoder are coupled to the input data multiplexer and to the output data multiplexer and also to a sign select logic circuitry. The sign select logic circuitry combines inputs from both decoders to control operation of the output multiplexer. The shifter has reduced part count and provides high-speed implementation along with greater flexibility for the user.
Arithmetic logic apparatus having two independent register files, one for each operand. Each register file has also associated therewith independently controlled incrementing and/or decrementing address mechanisms. Each such register file is coupled for addressing on a digit, byte or word basis. Operation of such apparatus is under the control of control instructions received from a control store included in a data processor in which such apparatus is also included.
An information processor is provided with a plurality of ALU chips under control of a microprogram and an ALU control circuit for controlling the ALU chips. The ALU control circuit responds to data bus information given thereto to select an ALU chip from which flag data is outputted. The ALU control circuit controls the ALU chip specified by the data bus information to operate it. When a carry is produced in the selected ALU chip, a carry generator is so controlled to produce a given carry signal toward a given ALU chip.
At least one parallel processor (PP or P-P) is connected between a central processing unit (CPU) interface and main memory for processing certain data simultaneously and synchronously with operation of the CPU. Integrated circuit apparatus for implementing the functions performed by the PP includes an arithmetic and logic unit (ALU), a set of registers, microprogrammable circuitry (RAM's, ROM's, PROM's) and other integrated circuitry. The PP includes decode and control apparatus, which decodes microinstructions stored in an extension to the control store of the CPU, the extension forming part of the CPU/P-P interface, and thereafter employs the decoded microinstructions to control operation of the P-P.
Multi-level indexed indirect addressing is provided with matched pairs of prefix bytes and suffix values which can surround any instruction. Each prefix code is distinguishable from an instruction code. Counters keep track of indirection levels.
