A so-called "programmable inverter" provides either a direct or an inverse signal path between its input and its output depending on a previously applied programming signal which is arranged to cause selective fusing of a fusible link. Such a circuit element may be incorporated in an input or an output of a logic gate so that a single type of gate may be programmed to perform a selected function from a number of functions.

Disclosed herein is a simple latched-fedback-memory finite-state-engine that produces an inherently stable output upon the receipt of a clock signal, that is synchronously or asynchronously generated. The finite-state-engine comprises at least three latches and a function module, wherein the output of one latch is used as an input for the function module and a previous output of the function module is re-entered as an input into the function module.

An LSI layout includes a logic function section and a series connection array of two MOSFETs, one end of which array is coupled to a power source voltage and the other end of which array is coupled to ground potential. A fixed logic output is produced at a junction point of the two MOSFETs by providing one MOSFET as an enhance-type MOSFET and providing the other MOSFET as a depletion type MOSFET. A logic circuit is provided which is connected with the junction point of the MOSFET array and with the logic section and is operable to couple the output of the logic section to an output side thereof. Two logic sections may be respectively associated with two logic circuits one of which is operable to couple the output of one logic section to an output thereof for its practical use and the other of which is operable not to couple the output of the other logic section to an output side thereof. The selection of the used section and the unused section is determined by the selection of either one of MOSFETs to depletion type. The LSI layout further may include a circuit section including MOSFETs. In that case, a single mask may be used in introducing a selected MOSFET of the MOSFET array and selected MOSFETs of the circuit section as depletion types. Such an LSI layout is suitable for the manufacture of many different kinds of LSI layouts with a minimized number of fabrication masks.

A configurable logic array comprises a plurality of configurable logic elements variably interconnected in response to control signals to perform a selected logic function. Each configurable logic element in the array is in itself capable of performing any one of a plurality of logic functions depending upon the control information placed in the configurable logic element. Each configurable logic element can have its function varied even after it is installed in a system by changing the control information placed in that element. Structure is provided for storing control information and providing access to the stored control information to allow each configurable logic element to be properly configured prior to the initiation of operation of the system of which the array is a part. Novel interconnection structures are provided to facilitate the configuring of each logic element.

A programmable logic device (PLD) is disclosed which can efficiently, in a real estate sense, emulate a Mealy state machine. Specifically, there is a PLD which has: (1) a programmable logical AND and two programmable logical OR arrays, similar to a field programmable logic array; and (2) one of the two fully programmable OR array generates a next state of the circuit and the second OR array generates an output responsive to both the inputs and the current state.