Video generator circuit for a dynamic digital television display

Claims

We claim:

1. A video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device, wherein the improvement comprises:

an ordered refresh buffer connected to receive said data and adapted to sort said data signals into groups ordered by extremal scan line position for the pattern represented;

an intermediate buffer having a first input connected to the output of said ordered refresh buffer for storing said ordered data signals once during each display field before the display of the pattern represented and outputting said ordered data signals in synchronism with the line scan of the display;

a graphical pattern generator connected to the output of said intermediate buffer for decoding said ordered data signals outputted from said intermediate buffer and generating on a first output line components of the pattern represented which lie along the display line to be scanned;

a partial raster assembly storage connected to said first output line from said graphical pattern generator to store the components of the pattern represented which lie along the display line to be scanned;

said graphical pattern generator modifiying said decoded ordered data signals to identify the horizontal coordinate for the intersection of said pattern represented with the next display line to be scanned, and outputting said modified data signal over a second output line to a second input line for storage in said intermediate buffer;

said graphical pattern generator omitting the output of a modified data signal on said second output line when no components of said pattern will intersect succeeding display lines to be scanned in said field.

2. The video generator circuit of claim 1, wherein said refresh buffer further comprises:

a threaded memory means connected to said host processor for receiving said data signals and a raster line address value;

said data signals containing a data portion, a pointer portion, and an end of thread portion;

said memory means being divided into a pointer index memory and a data signal memory;

said index memory connected to a first input line for accepting raster line values outputted from said host processor, for storing queue pointer addresses at locations corresponding to the raster line value, said pointer addresses specifying the location in the data signal memory of the head of the corresponding thread of data signals;

said index memory connected to said data signal memory for accessing the head of the thread for the corresponding data signals stored therein;

said data signal memory having a second input line connected to said host processor for storing a sequence of data signals in a threaded queue corresponding to the raster line value input on said first input line;

said gueue pointer addresses stored in said index memory being the location of the first data signal in the queue, each data signal in the queue containing in its pointer portion, the address of the next data signal in the queue, and the last data signal containing an end of thread indicium in its end of thread portion;

said data signal memory connected to an output data line for outputting data signals to said intermediate buffer in threaded gueues of common raster line value;

an end of thread signal detector connected to said output line of said data signal memory;

said threaded queue of data signals being read out of said data signal memory until said end of thread signal detector detects a data signal containing an indication in the end of thread portion that no further data is contained in the data signal memory, corresponding to the raster line value input on said first input line.

3. A video generator circuit for converting randomly occurring data signals received from a host processor, wherein the refresh buffer of claim 2 further comprises:

a next empty register connected to said data signal memory means for storing the location of the head of the thread for the queue of empty registers in said data signal memory;

control means connected to said next empty register and said data signal memory for threading each emptied location in said data signal memory by means of storing its address in said next empty register as the next head of the thread of empty locations and by storing the address of the rest of the thread in said emptied location.

4. A video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scan display device of claim 2, wherein said refresh buffer further comprises:

refresh counter means having a control input connected to said intermediate buffer and responsive to a data request by said intermediate buffer, for generating a raster line value to serve as an address for accessing a corresponding threaded queue of data signals from said memory means to be outputted to said intermediate buffer;

means for substituting said raster line value for the contents in said pointer portion of each of said data signals outputted by said memory means to said intermediate buffer.

5. The video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device, claim 1, wherein said intermediate buffer further comprises:

a random access memory for storing data signals;

said random access memory being divided into a preload memory and an active memory;

said preload memory having said first input connected to said refresh buffer and an output connected to the input of said graphical pattern generator, for storing said data signals when they are initially input to said intermediate buffer for the display of the pattern represented;

said active memory having said second input connected to said second output line of said graphical pattern generator and an output connected to the input of said graphical pattern generator, for storing said data signals modified by said graphical pattern generator to represent the portion of the pattern which remains to be displayed.

6. A video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device, of claim 5, which further comprises:

a raster sync pulse generator for specifying the time at which each raster line is to be displayed;

and wherein said intermediate buffer further comprises:

a next Y-line register connected to said first input line to store the raster line value of the first data signal in the corresponding threaded queue of data signals input from said refresh buffer;

a first comparator having an input connected to said next Y-line register and an input connected to said raster sync pulse generator, to determine when data stored in said preload memory is to be outputted on said output line to said graphical pattern generator for display;

a read counter having a control input connected to said preload memory for counting the number of data signals read from said preload memory and outputted to said intermediate buffer;

a write counter having an input connected to said preload memory for counting the number of data signals written into said preload memory from said refresh buffer;

a second comparator having a first input connected to said read counter and a second input connected to said write counter for determining when said preload memory has attained its maximum storage capacity in storing data signals.

7. The video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into time sequential video signals for use with a sequentially line scan display device of claim 6, wherein said intermediate buffer further comprises:

a last address written register having an input connected to said write counter for storing the number of data signals written into said active memory at the end of the last raster line scanned;

a third comparator having an input connected to said last address written register and said read counter to determine when all of the data signals in said active memory have been read and outputted to said graphical pattern generator;

a positive output from said third comparator causing said first comparator to determine whether additional data signals have been stored in the preload memory corresponding to the present raster line scanned.

8. A video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scan display device, of claim 5 wherein the improvement further comprises:

a raster timing generator which generates a periodic pulse;

and wherein said intermediate buffer further comprises:

a blink generator means having an input connected to said timing generator and an input connected to said first input line for said intermediate buffer and a control output line connected to said random access memory;

said data signals input over said first input line containing a blink portion to indicate that the corresponding graphical pattern is to be periodically displayed in synchronism with the periodic pulse from said timing generator;

said blink generator detecting said blink portion of a data signal input over said first input line and outputting over said control output line a control signal to said random access memory to load said data signal therein if said periodic pulse is on and to omit the loading of said data signal if said periodic pulse is off.

9. A video generator circuit for converting randomly occurring data signals received from a host processor representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device, of claim 1 wherein said graphical pattern generator further comprises:

a symbol memory having an input connected to the output of said intermediate buffer for storing symbol patterns having n raster line components;

said data signals input from said intermediate buffer having a symbol data portion and a segment code portion;

said symbol data portion of said data signal accessing the corresponding symbol pattern stored in said symbol memory;

said segment code portion representing which one of said n raster line components of said symbol is to be displayed;

a segment counter having an input connected to said output of said intermediate buffer for receiving said segment code portion of said data signal, and an output connected to said symbol memory, to select which of said n raster line components is to be displayed for the symbol pattern designated by said symbol portion of said data signal;

said segment counter modifying the contents of said segment code portion of said data signal to designate the next one of said n raster line components which is to be displayed;

said symbol memory having an output connected to said partial raster assembly storage for outputting the pattern of said selected raster line component of said accessed symbol pattern;

said segment counter having an output connected to said second input of said intermediate buffer for outputting said modified segment code portion of said data signal to form a modified data signal for storage in said intermediate buffer.

10. A video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device, of claim 9 wherein said graphical pattern generator further comprises:

said segment counter selecting a plurality of raster line components of said symbol pattern for display;

said segment counter modifying the contents of said segment code portion of said data signal to designate the next plurality of said raster line components to be displayed;

said symbol memory outputting said plurality of raster line component patterns to said partial raster assembly storage.

11. A video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scan display device of claim 9, which further comprises:

a plurality of partial raster assembly storage units, each of which displays a separate primary color;

and said graphical pattern generator further comprising:

said data signal having a color portion designating in which of a plurality of colors the symbol is to be displayed;

a color switch means having an input connected to the output of said intermediate buffer for receiving said color portion of said data signal and switching the output of said symbol memory to the designated ones of said plurality of partial raster assembly storage units; whereby the symbol may be displayed in a selected color.

12. A video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device of claim 9, wherein said graphical pattern generator further comprises:

a segment detector having an input connected to said segment counter, for detecting when said modified segment code portion indicates the last raster line component of said symbol has been accessed from said symbol memory;

said segment detector having a control output connected to said intermediate buffer to prevent a modified data signal from being input to said intermediate buffer over said second input line when the last raster line component of said symbol has been accessed from said symbol memory.

13. A video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned displayed device of claim 9, which further comprises:

a plurality of partial raster assembly storage units, each of which displays a separate intensity;

and said graphical pattern generator further comprises:

said data signal having a color portion designating in which of a plurality of intensities the symbol is to be displayed;

a color switch means having an input connected to the output of said intermediate buffer for receiving said color portion of said data signal and switching the output of said symbol memory to the designated one of said plurality of partial raster assembly storage units;

whereby a symbol may be displayed at a selected intensity.

14. A video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned displayed device of claim 1, wherein said graphical pattern generator further comprises:

said graphical pattern generator generating a sequence of connected horizontal line segments on successive raster lines to simulate a vector to be displayed;

said data signal input from said intermediate buffer representing said vector with the abscissa of its origin represented by an X portion and its reciprocal slope represented by a reciprocal slope portion;

an X address register having an input connected to the output of said intermediate buffer for receiving said X portion of said data signals and having an output connected to said partial raster assembly storage for locating the abscissa of the origin of a first one of said horizontal line segments representing said vector;

a slope register having an input connected to the output of said intermediate buffer for receiving said reciprocal slope portion of said data signal;

an adder having an augend input connected to said X address register and an addend input connected to said slope register for outputting a sum representing the value of the abscissa of the origin of the next one of said horizontal line segment representing said vector on the next raster line;

said adder having an output line connected to said second input of said intermediate buffer for outputting said sum as a modified X portion of said data signal for storage in said intermediate buffer.

15. The video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device of claim 14, wherein said graphical pattern generator further comprises:

said data signal input from said intermediate buffer having a raster line portion representing the number of raster lines upon which said vector will be displayed;

a raster line counter having an input connected to the output of said intermediate buffer for receiving said raster line portion of said data signal;

said raster line counter modifying the contents of said raster line portion of said data signal to designate the number of remaining raster lines upon which the remaining portion of the vector is to be displayed after said instant horizontal line segment is displayed;

said raster line counter having an output connected to said second input of said intermediate buffer for outputting said modified raster line portion of said data signal to form a modified data signal for storage in said intermediate buffer;

a zero detector having an input connected to the output of said raster line counter for detecting when said modified raster line portion equals zero indicating no further components of the vector to be displayed need be generated.

16. The video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device of claim 14, wherein said graphical pattern generator further comprises:

a length register having an input connected to said slope register for storing numerical value representing the length of said horizontal line segment;

a length decoder means having an input connected to said length register and an output to said PRAS, for generating a sequence of raster display data representing said horizontal line segment.

17. The video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device of claim 16, wherein said graphical pattern generator further comprises:

said raster display data generated by said length decoder means being output in a sequence of n bit units to said PRAS;

said raster line being divided into units of n-bits in length with modulo n=0 boundries;

said length decoder means having an input connected to said X address register;

said length decoder means dividing the X address from said X address register, modulo n, leaving a remainder;

said length decoder means subtracting said remainder from n, leaving a difference;

said length decoder means comparing said difference with the length of said horizontal line segment from said length register;

said length decoder means outputting as a first unit of raster display data, a number of bits corresponding to said difference if said difference is less than said length or a number of bits corresponding to said length if said length is less than said difference;

said length decoder means outputting n-bits as a next unit of raster display data and subtracting the value of n from said length, leaving a residual length until the value of said residual length is less than n;

said length decoder means dividing the sum of said X address and said length modulo n, leaving a second remainder;

said length decoder means outputting as a last unit of raster display data, a number of bits corresponding to said second remainder.

18. The video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned device of claim 17, wherein said graphical pattern generator further comprises:

said raster line being divided into blocks of mxn - bits in length with modulo mxn =0 boundries;

said length decoder means dividing the X address from said X address register, modulo mxn, leaving a third remainder;

said length decoder means subtracting said third remainder from said length leaving a second difference;

said length decoder means dividing said second difference modulo nxm leaving a quotient;

said length decoder outputting on a second output line to said PRAS, raster display data indicating the number of contiguous mxn bit blocks representing said horizontal line segment is equal to said quotient.

19. The video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device of claim 1, which further comprises:

said partial raster assembly storage having a first line buffer and a second line buffer, which are alternately loaded with raster display data from said graphical pattern generator and are alternately read out for display.

20. A video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device, wherein the improvement comprises:

a threaded buffer connected to receive said data and adapted to sort said data signals into groups ordered by extremal scan line positions for the pattern represented;

an intermediate buffer having a first input connected to the output of said threaded refresh buffer for storing said ordered data signals once during each display field before the display of the pattern represented and outputting said ordered data signals in synchronism with the line scan of the display;

a graphical pattern generator connected to the output of said intermediate buffer for decoding said ordered data signals outputted from said intermediate buffer and generating on a first output line components of the pattern represented which lie along the display line to be scanned;

a partial raster assembly storage connected to said first output line from said graphical pattern generator to store the components of the pattern represented which lie along the display line to be scanned;

said graphical pattern generator modifiying said decoded ordered data signals to identify the horizontal coordinate for the intersection of said pattern represented with the next display line to be scanned, and outputting said modified data signal over a second output line to a second input line for storage in said intermediate buffer;

said graphical pattern generator omitting the output of a modified data signal on said second output line when no components of said pattern will intersect succeeding display lines to be scanned in said field.

FIELD OF THE INVENTION

The invention disclosed herein relates to data processing devices and more particularly relates to digital television display systems.

BACKGROUND OF THE INVENTION

Digital television display systems in the prior art produced line drawings by storing one video bit for every element of the picture. In many such prior art systems the raster assembly storage would have to store as many as one million video bits for a 1024 X 1024 raster matrix. The completed picture would then be transferred to a refresh store. One substantial drawback in such prior art displays is that any alteration in the displayed picture would require either the generation of a new picture or the moving of all one million bits to the raster assembly storage for modification and return. Thus to effect a single erasure of a single vector would require either the reassembly of the entire raster or the transfer of the entire one million bits out of the storage for alteration and replacement. In the event that two vectors cross one another, the process of erasing a first vector, after transfer back to the assembly store, would remove video bits common to both vectors, leaving the remaining vector with a gap separating the components on either side of the erased vector.

Some progress has been made in the prior art through the implementation of queue memories for the storage of digitally encoded video data. One example of such a prior art system discloses a video generator for data display which employs a threaded refresh buffer. The use of such a buffer permits a reduction in the size of the raster assembly storage over that of the prior art. However, this prior art image buffer must be large enough to accommodate the tallest character which is intended to be displayed. According to prior art teachings this would be at least eight raster lines which must be stored in the video image buffer. The prior art states that if a vector were to exceed the vertical height of such a video image buffer, it would have to be generated as separate segments. This, it is disclosed, would be accomplished by returning the contents of vector registers in the vector generator to the threaded list of the data buffer in order that the vector generator may continue at a later time in the scanning sequence. It is seen that the amount of processing necessary to access the next component of the vector in the next group of raster lines to be scanned, by accessing the threaded buffer itself, reduces the display capability of the system and increases its complexity.

What the art requires is an improved means of accessing subsequent components of vectors and other data stored in the system so as to enable higher rates for display.

OBJECTS OF THE INVENTION

It is an object of the invention to store graphic and alphanumeric display data so as to be more efficiently accessed than has been capable in the prior art.

It is another object of the invention to store graphic display data so as to retain its identity and special attributes such as color, intensity or blink, in an improved manner.

It is still another object of the invention to display decomposed graphics as vector segments in an improved manner.

It is still a further object of the invention to store graphic display words loaded in a random sequence, so as to be sorted into threaded queues of sequential raster line location, in an improved manner.

It is still a further object of the invention to cyclically store display data which is continually modified as the raster field is generated.

SUMMARY OF THE INVENTION

A video generator circuit is disclosed for converting randomly occurring data signals representing graphical patterns into a time sequential video signal for use with a sequential line scan display device. The improvement of the invention includes a threaded buffer connected to receive the data signals and adapted to sort the data signals into groups ordered by extremal scan line positions for the pattern represented. An intermediate buffer having a first input connected to the output of the threaded refresh buffer, stores the ordered data signals once during each display field before the display of the pattern represented. The intermediate buffer outputs the ordered data signals in synchronism with the line scans of the display. A graphical or alphanumeric pattern generator is connected to the output of the intermediate buffer for decoding the ordered data signals outputted from the intermediate buffer. The graphical pattern generator generates on a first output line, components of the pattern to be represented which lie along the display line or group of lines to be scanned. A partial raster assembly storage is connected to the first output line from the graphical or alphanumeric pattern generator to store the components of the pattern represented which lie along the display line or lines to be scanned. The graphical pattern generator modifies the decoded, ordered data signals to identify the horizontal coordinates for the intersection of the pattern represented with the next display line or lines scanned. The graphical or alphanumeric pattern generator also modifies control data and outputs the modified data signals over a second output line to a second input line in said intermediate buffer for storage. The graphical or alphanumeric pattern generator omits the output of a modified data signal on the second output line when no components of the pattern will intersect succeeding display lines to be scanned in the field. The intermediate buffer has a novel memory structure organized into a preload area and an active area. In operation, the video circuit generator invention reduces the amount of processing necessary to dynamically generate a DTV display.

DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.

FIG. 1 depicts the video generator circuit invention.

FIG. 2 shows the data word format input to the refresh buffer 28.

FIG. 3 shows a detailed block diagram of the refresh buffer 28.

FIG. 4 shows a detailed block diagram of the intermediate buffer 38.

FIG. 5 is a block diagram of the symbol generator 40.

FIG. 6 is a detail block diagram of the vector generator 42.

FIG. 7 is a block diagram of the partial raster assembly store 44.

FIG. 8 depicts a system block diagram of a dynamic digital television display system.

FIG. 9 is a block diagram of a graphic display control unit 8.

FIG. 10 shows a wiring diagram of the display adapter interface.

FIG. 11 shows a threaded list in the refresh buffer for a first loading.

FIG. 12 shows a threaded list in the refresh buffer for a second loading configuration.

FIG. 13 shows the refresh buffer-intermediate buffer interface.

FIG. 14 is a block diagram of the addressing logic for the intermediate buffer.

FIG. 15 shows an implementation of the timing for the intermediate buffer.

FIG. 16 shows the preload addressing logic 94.

FIG. 17 is a timing diagram for sequential symbols.

FIG. 18 is a simplified block diagram of the vector generator 42.

FIG. 19 is an example of the operation of the vector generator 42.

FIG. 20 gives a detailed illustration of the timing for the refresh cycle in the PRAS.

FIG. 21a shows the SYNC generator block diagram and FIG. 21b, the resulting raster.

DISCUSSION OF THE PREFERRED EMBODIMENT

The dynamic digital TV display technique can be generally described as follows. Digital TV is a display technology which takes coded data from a computer source and converts it to a TV video signal. This signal drives one or more TV monitors which present the desired computer display picture. The logic which converts the coded computer data to a TV signal is all digital, the same as that used in a computer. Thus, digital TV has succeeded in using the technical advances developed in both the TV and computer industries to provide a unique computer display capability.

A TV display in the context used here is one in which the electron beams (one for each primary color) are repeatedly deflected across the face of the Cathode Rav Tube (CRT) in a series of closely spaced parallel lines (called a raster). This is repeated a fixed number of times each second (refresh rate). Within a particular display system the number of parallel lines and the refresh rate are usually fixed. A typical display has 525 lines and is refreshed 30 times per second. Each frame is divided into two fields. One field consists of the odd numbered scan lines and the other the even scan lines; this results in an interlaced scan which produces an apparant doubling of the refresh rate.

Digital TV presents a computer display in a TV format by reducing the image to a matrix of points or display elements. In a display with horizontal scan lines, the number of vertical display elements is equal to the number of visible scan lines. The number of elements within each scan line is somewhat arbitrary but is chosen to be 1.33 times the number of scan lines. This conforms to the 4:3 aspect ratio of the TV Cathode Ray Tube. Even though the image is made up of elements, it appears continuous because of the large number of elements used.

The invention disclosed herein makes use of the new technique of graphic generation known as "on-the-fly" or "implicit refresh". This is to be contrasted from the "explicit refresh" found in older DTV Systems. The on-the-fly technique permits all displayable data to retain its identity in computer coded form up the the final stages of video generation.

In use, implicit refresh allows for erasing data on the display without erasing overlaying (intersecting) data. It permits selective modification of the data. This method of display generation is particularly attractive when blink (flash) and color are desired. The attribute bits for indentification or color and flash are contained in computer coded form.

In terms of hardware, implicit refresh can reduce the storage requirements in memory by a factor of 18 to 1 for a color graphic display.

The video generator circuit invention shown in FIG. 1, makes use of the "on-the-fly" refresh technique to dynamically generate a digital television display. The video generator circuit is composed of the refresh buffer 28, the intermediate buffer 38, the vector generator 42 or symbol generator 40, and the partial raster assembly store 44.

The refresh buffer 28 accepts data signals representing picture elements, in a format such as is shown in FIG. 2 from a data source such as a computer or programmable controller. The refresh buffer 38 reads the data words out, ordered by Y-address, once per field to the vectors and symbols organized as background and dynamic data. The refresh buffer 28 consists of a control module and two storage modules providing a total of 8K halfwords, each with sixteen data and two parity bits. The major function of the refresh buffer 28 is to store the coded data for constructing the visual display. Data, which is received from the digital computer over line 68 in random fashion, is stored in a form ordered by Y-line. This allows the refresh buffer 28 to be read on a line-by-line basis. A detailed block diagram of the refresh buffer is shown in FIG. 3.

The data word formats, shown in FIG. 2 consist of the Vector Format, the Symbol Format, the Index Format, and the Empty Slot