An initial input list in a series of sequential dependent input lists is clocked through a first sort stack and written into a first buffer as Q groups of P numbers each. The P numbers are in numerical order within each group with the smallest number in the first location of each group. The first number in each group is loaded into a second sort stack which arranges them in numerical order, causing the smallest number in the input list to form the first number in the initial output list. A replacement number is numerically sorted into the second stack from the Q groups each time the smallest remaining number is clocked out. Each replacement number is from the next location of the same Q group as the most recently clocked out number. Thus, the smallest remaining number in any of the Q groups of the first buffer is always available to the second stack and appears as the smallest remaining number in the second stack is always in the first location of the second stack. As the contents of the first buffer are inserted in to the second stack, the first sort stack processes a next input list into a second buffer. The buffers read and write in overlap manner permitting both sort stacks to process input lists simultaneously. As each smallest remaining number of the initial list becomes available at the output of the second stack, it may be updated and returned to the input of the first stack as an element of the subsequent dependent list. The double buffer overlap operation approximately doubles the throughput rate and permits updating of the dependent lists.

A decoder used for graphic processing or the like. The decoder includes a first input unit for inputting coordinates of two points, a second input unit for inputting a direction between the two points, and an operation unit for logically operating a relationship between the two points utilizing a symmetry of coordinates on the basis of data supplied from the first and second input units. According to the decoder, the scale of the circuit can be reduced.

A microprocessor based data processing system including a microprocessor, a memory unit, and display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.

A visual display system and method for use in converting calligraphic symbology information into raster scanned symbology. The system simultaneously generates and displays calligraphic and raster matrix imagery utilizing the same set of software instructions. The imagery is displayed upon a single, hybrid calligraphic/raster matrix display or separate raster matrix and calligraphic displays. A programmable calligraphic symbology generator utilizes digital stroking techniques that successively generates addressing for a matrix arrayed memory and determines the attributes of both the raster matrix generated and calligraphic generated symbology. The information is stored in a single or a plurality of matrix arrayed memories according to desired symbol attributes and system performance.

A memory controller, in one embodiment of the present invention, can control the execution of a memory maintenance operation. A screen blanking event counter can output a first signal. A memory maintenance state circuit can be coupled to the screen blanking event counter to receive the first signal. The memory maintenance state circuit can output a memory maintenance enable signal.