A phase comparator which comprises a differential amplifier; and a first and a second active load circuit each comprising a current mirror circuit and from which is derived an output signal which is reversed in phase with respect to the output of the differential amplifier. The outputs of the respective active load circuits are superimposed upon each other through other current mirror circuits, and an output resulting from the superimposition is alternately provided based on rectangular waveform signals which are reversed in phase with respect to each other. By smoothing the output, a DC output corresponding to the phase shift of input signal from the rectangular waveform signals is produced. The phase comparator comprises a combination of transistors and diodes which are cascode-connected to each other, and thus is operable with a predetermined voltage as low a 1 V or less.

A digital signal transmission system in which a pulse code modulated (PCM) signal is retimed in a regenerator using a decision circuit supplied by a clock, the frequency of which is half that of the bit rate (typically 1 Gigabit/second), and is demultiplexed using multiplexers clocked at a frequency half that of the bit rate. In each case the clock frequency is derived from the data stream using a clock extractor. A voltage controlled oscillator (VCO) generating a signal at substantially half the bit rate is connected to one input of a phase detector to another input of which is connected to receive current pulses representing transitions in the incoming data signal. The phase detector comprises first, second and third pairs of long tailed-pair connected transistors, the collectors of the transistors of the first pair of being connected respectively to the common connected transistors of second and third pairs. A first delay circuit providing a delay of approximately a quarter of a period of the VCO is connected between the base electrode of one of the first pair of transistors and the base electrode of one transistor of each of the second and third pairs of transistors. A second delay circuit of the same period as the first delay circuit is connected between the base electrode of the other of the first pair of transistors and the base electrode of the other transistor of each of the second and third pairs of transistors.

A voltage controlled oscillator includes an emitter coupled multivibrator in which a capacitor determines the frequency of oscillation along with a pair of load resistors and a pair of current sources. A differential amplifier is coupled to operate in parallel with the mutlivibrator and its tail current is operated differentially, with respect to the currents in the pair of sources, in response to the input voltage at a first modulation input port. Thus, a constant current flows in the multivibrator loads even when the frequency is modulated. A second input port is coupled to vary the tail current in the differential amplifier to comprise a dual port control of the voltage controlled oscillator. The circuit can be operated at a relatively low supply voltage and can be temperature compensated. Furthermore, the input ports can include circuitry having a logarithmic response for digital signaling processing.

A slowly varying bias signal is added to one input of a Wave Form Transition Sequence Detector, as more fully described in a related application cited herein, to provide a differential output therefrom which is directly proportional to the time between transitions occurring on two input wave forms. The slowly varying bias modulates the level of one input wave form, and thereby varies the time required for the Wave Form Transition Detector to detect a transition occuring thereon. By symmetrically varying the response time of the Wave Form Transition Sequence Detector to one input wave form in the neighborhood of the occurrence of a transition on the second input waveform, the average differential output of the Wave Form Transition Sequence Detector over a cycle of the slowly varying bias level will be proportional to the time between transitions occurring on the two input wave forms.

Offset canceling amplifier circuit in which a high accuracy of output with a suppressed output offset is achieved and a variation in a slew rate is also suppressed, and a display device having the amplifier circuit. A first differential pair (M5, M6) connected between a first current source (M9) and a common load circuit (M1, M2) and a second differential pair (M3, M4) connected between a second current source (M8) between the common load circuit (M1, M2) are provided. A switch (SW1) connected between one input of the first differential pair (M5, M6) and an input terminal (1), a switch (SW2) connected between the one input of the differential pair (M5, M6) and an output terminal (2), a switch (SW3) connected between one input of the second differential pair (M3, M4) and the output terminal (2), and a capacitance element (C1) connected to the one input of the second differential pair (M3, M4) are provided. The other input of the first differential pair (M5, M6) is connected to the input terminal (1), and the other input of the second differential pair (M3, M4) is connected to a reference voltage input terminal (3). An amplifying operation by an amplifying element (M7) is performed responsive to a common output signal of the two differential pairs, and circuits (SW11, SW12) for controlling activation or deactivation of at least one of the first and second current sources are provided.