An address recall system coupled to a processor to permit operator examination of a predetermined number of executed system addresses. A processor system address is manually inserted to the recall system. When a system address being executed compares with the operator address setting, an address equality signal is generated. The recall system logic generates either a stop or interrupt state for the processor responsive to actuation of another manually operated input switch. Addresses being executed by the processor are stored in a push down memory stack within the recall system. When an address equality signal is generated, one or more of the consecutively executed addresses contained in the memory stack may be manually displayed in the reverse order of execution.
A program history (P-history) listing of branch-type instruction addresses for pipelined data processing system that employs one or more pipelined processors is stored in a random access memory (RAM) which is also used to store other executive or task information. A set of three queue registers is used to respectively store, 1) the absolute "to" address to which a branch instruction will jump, 2) the relative "to" address, to which the branch instruction will jump, and 3) the relative "from" address, from which the branch instruction will jump. The queues allow the storage of the P-history in the RAM without interference with the use of the RAM by the other functions that access it and without interruption of the pipelined processor.
An apparatus for maintaining a history of instructions which have been most recently executed by a digital computer. A push-down stack is utilized for storing the contents of the program address counter, or the operand portion of the instruction register, of the computer upon the execution of every instruction and then pushing down the push-down stack whenever the last instruction executed by the digital computer was a branch type instruction. Provision may also be made for addressing the push-down stack so that the contents thereof may be reviewed in the order opposite from which it was loaded. This apparatus allows a user or diagnostic program to have access to the address of the most recently executed branch type instructions. In this way, a history of the most recently executed instructions can be maintained to aid hardware and software diagnostics.
A data processing apparatus in which a memory (10) is accessed at addresses stored in an address regiser (20). An incrementation circuit (38) successively increments or decrements the address stored in the principal register, under the control of an address cycling circuit (22). A pair of auxiliary registers (30, 35) respectively store the minimum and maximum address values to be reached in the principal register, and a comparison circuit (37) determines when the address therein matches the minimum or maximum value. The address cycling circuit, together with the comparison circuit, loads the principal register with the minimum address value when the address therein reaches the maximum value, the address therein thereafter being decremented, and loads it with the maximum address value when the address therein reaches the minimum value, the address therein thereafter being incremented. Such operation is particularly useful for preforming the functions of a fixed or adaptive transversal filter for data transmission, the data stored in the memory being the filter coefficients.
Diagnostic circuitry for use with the processor of a data processing system. The diagnostic circuitry includes a control register execution log for receiving control store addresses from a control register associated with an "EXECUTE+1" stage. A log pointer addresses the log when control store addresses are written into or read from the log. Test registers connected to the log and log pointer provide control store addresses and decrementing log addresses when the contents of the log are examined. One of the test registers is also used to hold a control store address for comparison with control store addresses of executing microinstructions, and when a match occurs, to generate a SYNC signal.
In data processing apparatus in which address and data are transferred by means of DMA through an address bus and a data bus, a coincidence circuit determines whether the address on the address bus coincides with an address designated by an address designation device, a latch circuit latches the data on the data bus when the coincidence is detected and stores the latched data, and an indicating device indicates the data stored in the latch circuit.
