A saturation-limited bipolar transistor device or circuit and a method of making same are provided which includes a merged NPN transistor and a PNP transistor structure formed so as to produce denser cells or circuits. A simple process is used to form the structure which includes a double diffused technique for making the PNP transistor. The PNP transistor has a double diffused emitter-base arrangement wherein the emitter is asymmetrically positioned with respect to the base so as to also serve as a contact for the base of the NPN transistor. The PNP transistor limits the input current by bypassing excess current to a silicon semiconductor substrate or chip. The structure includes an N type epitaxial layer formed on an N type subcollector with a P type region provided near the surface of the epitaxial layer. The epitaxial layer serves as the NPN collector and as the PNP base contact region. A first N type region is formed through the P type region extending from the surface of the epitaxial layer to the subcollector dividing the P type region into first and second sections which serve as the PNP collector region and the NPN base region, respectively. A second N type region is formed in the second section of the P type region at the surface of the epitaxial layer acting as the NPN emitter and a P+ region is formed in the first N type region at the surface of the epitaxial layer extending into the second section of the P type region which forms the NPN transistor base. This P+ region serves as the PNP emitter and as the NPN base contact.

A compact integrated logic circuit having an inverter transistor and several coupling diodes adjoining the collector region of said transistor. Current is applied to the base of the transistor which forms the signal input. The inverter transistor has additional means by which an effective complementary auxiliary transistor is incorporated which dissipates a considerable part of the base current in the case the inverter transistor is overdriven so that the charge storage in the inverter transistor is restricted and controlled and by which a Schottky clamp diode across the base-collector junction of the inverter transistor can be avoided.

An integrated circuit overload protection device is used to protect a bipolar transistor used in the common emitter configuration. The protective device comprises a bipolar transistor of opposite type to the protected amplifying transistor. The protective transistor is connected with its base to the collector of the amplifying transistor and with its collector connected to the terminal of the power supply which is not connected to a terminal of the load resistor of the protected device. The emitter of the protective device is preferably connected to the base of the protected device through a protective resistor. Inputs to the protected transistor are provided at the interconnection of the emitter of the protected device with one terminal of the protective resistor.