A propagation line adder may be fabricated by replicating a unit circuit along a sense and reference propagation path. Each unit circuit corresponds to bits of the same order of magnitude of the binary addends. Selected segments of the sense propagation path are set a specified logical potential value and are coupled according to control signals generated within the unit circuit in response to the addend bits. The reference propagation path is then discharged and a sense amplifier, coupled to each segment of the reference and sense propagation paths, detects the state on corresponding segment of the sense propagation path. The propagation line adder implements an algorithm which produces the binary sum of two numbers by complementing the exclusive-or function of the addends according to a shifted product function. The shifted product function includes a carry in bit as its lowest order bit.
The semiconductor integrated circuit device includes a select gate for selectively transmitting a signal. The select gate includes a first gate for receiving and transferring a first logic signal to an output node, and a second gate for receiving and transferring a second logic signal to the output node. The first and second gates turn on complementarily to each other. The first gate has an output load capacitance viewed from the output node less than that of the second gate. The first gate receives, as the first logic signal, a signal not required to be transmitted at a high speed, or a signal of a predetermined logic level or a fixed level. The second gate receives, as the second signal, a signal to be transmitted at a high speed. Since the second gate has a less output load capacitance, the second gate is allowed to transmit a signal at a high speed.
A propagation line adder may be fabricated by replicating a unit circuit along a single sense propagation path. Each unit circuit corresponds to a bit of the same order of magnitude of the binary addends. Selected segments of the sense propagation path are set at a specified logical potential value and are coupled according to control signals generated within the unit circuit in response to the addend bits. A sense amplifier, coupled to each segment of the sense propagation paths, detects the state on corresponding segments of the sense propagation path. The propogation line adder implements an algorithm which produces the binary sum of two numbers by complementing the exclusive-or function of the addends according to a shifted product function. The shifted product function includes a carry-in bit as its lowest order bit.
A signal generator for generating mask signals includes a plurality of conductors 0 thru N respectively; each of the conductors is coupled through a respective resistive means to a first voltage bus; first, second, third, . . . groups of transistors of a first set respectively couple conductors 1 thru N, 2 thru N, 3 thru N, . . . N to a second voltage bus; first, second, third, . . . groups of transistors of a second set respectively couple conductors 0, 0 thru 1, 0 thru 2, . . . 0 thru N-1 to a second voltage bus; and decoders turn on the transistors of a selectable group of the first set and a selectable group of the second set in response to externally generated codes CD#1 and CD#2.
A digital adder module has a carry-in terminal, N pairs of data terminals, N sum terminals, and a carry-out terminal. A high-speed low-capacitance carry bypass signal path couples the carry-in terminal to the carry-out terminal. In one preferred embodiment, the capacitance of the bypass path is due solely to one transistor channel plus one transistor drain plus one internal logic gate plus interconnections between them.
A carry-save propagate adder employing two exclusive-OR blocks, a multiplexer block for selecting between a carry propagate input or a carry-save input, and a further multiplexer block for supplying as a carry-save output either the carry-save input or one of the data inputs.
