Priority interrupt apparatus includes a level priority network, a plurality of priority networks, and selector circuits, each corresponding in number to the number of channel sources operative to generate interrupt requests. Each priority network receives requests signals corresponding to different types of possible event signals requiring attention and produces a type code designating the highest priority event from the channel associated therewith. The priority is established in accordance with a preassigned event priority approximating the priorities assignable by program. Each of the selector circuits is connected to receive as a control input the type code signals generated by the priority network associated therewith. Additionally, each selector circuit receives a different set of interrupt level number signals representative of priorities assigned by program to the number of possible event signals. In response to the request signals, the selector circuit of each channel source applies as an input to the level priority network the programmed designated set of interrupt level number signals specified by the type code signals. The level priority network includes a number of compare circuits and output gating circuits. Each compare circuit provides signal indications as to which one of a pair channels has the higher priority event as defined by the selected interrupt level signals. Signals indicating the results from each compare circuits are then applied to the output gating circuits which generate a code for selecting the type code and interrupt level signals of the channel source receiving the highest priority event.
Multiple stations exchange information without central supervision. Stations requiring a cycle of access time on a shared time-divided bus participate in a cyclic access resolution process. The station having highest priority for a next bus cycle indicates its precedence to the other stations, and assumes exclusive use of the bus in the next cycle. The bus may comprise separate sections for data and response communications. Separate access resolution processes are conducted relative to each section. After gaining access to the bus for one cycle of data transfer a station becomes ineligible to compete for access to the data section until it receives an associated response. Accordingly receiving stations may control both the rate of data transmittal and the rate of access competition activity at associated origin stations. The data and response communications may include address information for enabling stations to intercommunicate directly in pairs. Data processing stations subject to multi-level interruption may present control signals designating acceptable interruption priority levels. Other stations seeking to interrupt such processing stations are eligible to compete for access to the bus only if assigned interruption priorities are at designated levels.
An interrupt expander circuit provides for greatly enlarging the capacity of vectored interrupts in a microprocessor system. This circuit provides the capability for a very large number of peripheral devices to be connected to a microprocessor centeral processing unit via an interrupt structure while maintaining the same interface requirements between the interrupting peripheral devices and the microprocessor. This circuit provides a priority interrupt structure.
An apparatus is included within the bus interface circuits of each processing unit of a multiprocessing system which connect in common with the other units of the system to an asynchronous system bus. The apparatus and interrupt signal couple to the processing unit's level register and interrupt circuits. In response to a command specifying a level change, the apparatus conditions these circuits to store level and interrupt signals applied to the system bus as part of such CPU command during a bus cycle of operation granted to the processing unit on a priority basis. This ensures the reliable switching between interrupt levels and the notification of such level changes to the other units of the system without interference from other processing units.
An interrupt interface circuit for interrupt level sharing comprising a pulse generator having an open-collector or tri-state output connected to an external interrupt line shared by other similar circuits. An active internal interrupt signal causes the pulse generator to pulse. The external interrupt line is fed back and latched on a disabling input of the pulse generator so that any pulse on the external interrupt line prevents further pulsing. The software handler of the interrupt, upon servicing an interrupt of the interrupt level, causes the enabling of the pulse generators of that level, thereby permitting active internal interrupt signals to produce a further pulse. By this interrupt level sharing, phantom interrupts are eliminated and servicing overhead is minimized. R
An apparatus and method for prioritizing interrupt requests in a RISC processor. By utilizing hardware to prioritize the requests, processor time is reduced. The acknowledge signal from a priority resolve circuit selects the given service routine entry to branch instruction generating circuit. A lower priority service routine can be interrupted by a higher priority request.
