A method and circuit arrangement for expanding the addressing capacity of a central unit, in particular of a microprocessor, beyond the address capacity given by the address stock of an instruction counter provides for the use of at least one base address of the central unit in order to bring about the emission of additional address bits which are combined with the address bits of the base address to form an extension address. The invention may be advantageously practiced in the central unit of a teleprinter private branch exchange.

A programmable control latch mechanism which is particularly useful in a microprocessor. One or more control latches are provided which can be set or reset under direct program control directly from the instruction register of a data processor by the loading therein of a unique program instruction. The unique instruction includes for each control latch two predetermined bit positions, one of which determines whether or not the control latch is to be changed and the other of which determines the binary value to which the control latch is to be changed. This enables anywhere from one to all of the control latches to be changed by a single instruction and enables each latch which is changed to be changed to any desired binary value. The control latch outputs can be used for storage page selection, direct control of external devices or circuits, selection of internal processor functions and the like.

Circuitry within a system memory controller of a data processing system enables an M-bit processor to address a memory location that requires an N-bit address, wherein N is greater than M. Thus, a less than 48-bit processor will be able to access IPL code resident within a 48-bit memory system. An M-bit address is received from a processor and then extended into an N-bit address with a mask of N-M bits. The extended address is compared with an N-bit address representing the memory location to be addressed, and the extended address is then selected to access the memory location when the extended address equals the N-bit address representing the memory location.

An addressing and control system for a mass memory which is partitioned into selectable pages of individually specified size. The invention generates a composite address for the mass memory so that a microcomputer of limited address size can access the mass memory by individually specified page. One circuit implementation utilizes a register to latch page size and selection information for subsequent combination with address information to generate a full address for the mass memory. In that situation, the size register multiplexes the address bus information and page selection information to maintain correspondence between the specified size of the page and the total addressing bits available. In another form, the invention provides for supplementing the number of address bus bits with bits transmitted over the data bus to extend the bit length of the address used to access the mass memory.

A Central Processing Unit (CPU) provides programmable autoloading of memory pointer registers. The CPU includes an op-code extension register (OER) to store a code specifying the autoloading status of each memory pointer register. Whether or not a particular memory pointer register is loaded at the end of an instruction cycle with an operand address carried by the current instruction depends on the binary state of a particular bit position in the OER corresponding to the particular memory pointer register. The contents of the OER can be changed by means of an instruction for transferring a new code to OER. A CPU architecture having an OER permits software specification of autoloading without significantly increasing the number of op-codes required to define the instruction set. Fewer op-codes generally permit shorter instructions. The advantages provided by shorter instructions are reduced memory overhead for program storage and increased processing efficiency in data processing systems having a small word size.