A circuit arrangement for a quartz controlled electrical clock comprising an oscillator stage a frequency divider separated from the oscillator stage by a gate controlled by a control logic unit, an output stage connected to the frequency divider and a stepping motor connected to the output stage, the control logic unit responding to a command signal to open the gate and disconnect the oscillator stage from the frequency divider with the frequency divider retaining its memory content at the instant of disconnection and with no current flowing through the drive coils of the stepping motor.
A time resetting operation in an electronic timepiece requires blocking of the stepping motor 1, and block of the mechanical type is avoided by the invention. A STOP switch 10 actuated by a time resetting stem of the timepiece sets to state "1" a flip-flop 11 which blocks gates 12 and 13 for controlling the passage of the pulses which drive the motor 1 through a feed circuit 2. The circuit 2 then passes a continuous current in the same direction as the last drive pulse. Thus, triggering of the continuous current leaves the position of the rotor unchanged. A counter 14 counts 1-second pulses and then resets the flip-flop 11, which causes the motor to resume normal operation. This avoids excessive discharging of the battery of the electronic timepiece if the user forgets to return the stem to its initial position after a time resetting operation.
