A method for generating object code which represents a conformance of input data structures into that of a prespecified output data structure such that at runtime data in the input structures can be embedded into the output structure. At least some of the input and output structures have some common fields but differ in the distribution of the hierarchical and repeated groups of said fields. The method utilizes graphical models for characterizing the prespecified forms and a series of operations based upon the difference in the complexity and distribution of the graphs for conforming the input structure to that of the output.

Improved apparatus for computing locations in compound data items and current lengths in varying-length compound data items when the elements in the compound data items and the varying-length data items have sizes which are powers of 2. The apparatus is used in a digital computer system wherein data items are represented by names associated with name table entry items in memory. The digital computer system's processor includes a name translator for calculating addresses and lengths using the name table entries associated with names. The name table entry associated with a name representing a compound data item or varying-length compound data item having elements whose size is an integer power of 2 includes an element size specifier which has as its value the exponent specifying the power of 2 equal to the size of the elements. When a name table entry for a compound data item includes such an element size specifier, the name translator calculates the displacement of an element in the compound data item or the length of a varying-length data item by shifting an index value specifying one of the elements or a current number of elements value specifying the number of elements currently in the varying-length data item to the left the number of times indicated by the integer value of the element size specifier.

A data merging program causes a computer to perform a step of selecting a first cell as a starting point of merging; a step of comparing a first numerical value, which is recorded in the first cell, with a preset reference value; a step of, if the first numerical value is smaller than the reference value, calculating a total value of the first numerical value and a second numerical value recorded in a second cell adjacent to the first cell in the same column; a step of comparing the total value with the reference value and, if the total value is smaller than the reference value, setting a third cell into which the first and second cells are merged and recording the total value in the third cell; and a step of selecting the third cell as a new starting point of merging.

The disclosure provides a general purpose register (GR) mask which associates predesignated address spaces with respective GRs assigned to contain a base value for calculating logical addresses within the address spaces. An address space mask register has a plurality of digit positions which receive the respective digit values comprising a particular GR mask. A respective digit position is selected by a base GR address signal provided by a storage address request from a CPU instruction decoder. The particular value of the selected digit in the mask register controls the selection among a plurality of STO registers, which designate a plurality of simultaneously available address spaces. The selected base GR is used in a System/370 B, D or X, B, D type of logical storage address representation. A base GR explicitly contains an intra-address-space base value. The GR mask assigns an implicit inter-address-space designation to the base GR in a simple manner which is handled by conventional address translation hardware. The available address spaces are respectively designated in STO registers by segment table addresses (called STOs). Any number of STO registers (and available address spaces) may be provided up to the radix of each digit in the GR mask. The executing program exists in the address space designated in one of the STO registers. A plurality of storage protect key registers are respectively associated with the STO registers to control the accessing authorized to the executing program within each available address space. The key value may be independently authorized and provided for each available address space. A cross-memory implementation results which enables a compatible extension of the IBM System/370 architecture by permitting the unrestricted use of all S/370 instructions including storage-to-storage (SS) instructions that can access data simultaneously in plural address spaces in non-privileged state.

Decision and control logic for use in digital computers that operate in cycles provides binary valued decision signals for effecting decisional control within the computer such as that utilized in conditional branching. The decision signals are provided in accordance with binary valued control functions of binary valued static and dynamic control variables utilized in the computer. The dynamic control variables are available in a computer cycle subsequent to the availability of the static variables and represent conditions of various components of the computer. Truth tables of the control functions are stored in logic function memories addressed by logic function selection control fields of computer control words, the control fields selectively addressing the truth tables in accordance with the desired functions. The static variables are utilized for addressing the logic function memories for providing the truth table entries corresponding to the selected function of the static control variables and the dynamic variables select among the addressed truth table entries to provide the binary valued decision control signals. Preferably the logic function memories are implemented by LSI integrated circuits.