A method is provided for generating electrical test patterns for testing functional AC parameters of integrated semiconductor circuits from the test patterns used for the more conventional testing of the DC parameters of such circuits. The AC parameters include such factors as rise time, fall time and circuit delays. Starting with a DC pattern known to be sufficient for the DC testing of the circuit to be tested, each increment of the DC pattern which comprises a plurality of parallel bilevel signals is applied to a corresponding plurality of input points in a standard of the circuit, preferably computer simulated. The resulting output is sensed at output points in the circuit standard. Then, one by one, the input signals in the applied increment are changed while the remainder of the signals are maintained at their original levels. When a change in one of the signals produces a corresponding change in the output, this is noted as path for AC testing. Then, there is stored as the first AC increment, a signal pattern wherein all the signals in the increments are maintained at their original levels except the input producing the change in output, which is stored as a pulsed signal. The procedure is repeated for a plurality of signals in the increment and for a plurality of remaining increments in the DC pattern until an AC signal pattern is developed in which all the input points in the circuit standard are pulsed at least once.
A respective threshold circuit is provided for defining upper and lower thresholds representing logic levels of signals occuring within integrated circuits. The chronological position of a signal edge and the steepness of the signal edge are defined with the assistance of the two thresholds.
A method for use in an in-circuit tester automatically determines which test sequences must be regenerated as a result of a board modification, and automatically regenerates only the test sequences affected by the modification.
In an IC testing apparatus which executes a function test and a DC test, a resistor having a high resistance is connected to the output side of a DC tester such that the connection of the resistor allows a function test to operate normally if the DC tester is left connected to the function tester, thus allowing the DC test to be interrupted into the execution of the function test to enable a concurrent execution of the function test and the DC test. As a result, the time required to change switches in the DC tester, for example, can be executed during the function test, thus preventing the time interval required to change the switches from increasing the time interval required for the test, thereby reducing the testing time interval.
In automatic test equipment the logical levels on certain of the test pins are set to 0 and 1 by corresponding flip-flops included in respective I/O logic circuits. The states of the flip-flops (as well as other factors) are controlled by commands read out of a control RAM which is of sufficient width to provide a 4-bit command on lines for each logic circuit. The available commands include NOP commands and change commands which toggle the states of the corresponding flip-flops. A relatively small number of addresses of the control RAM have change commands entered in correspondence with selected ones of the pins. By repeatedly reading out the commands in these addresses in a non-cyclic sequence it is possible to generate a succession of different states of the flip-flops in the logic, which succession is much longer than the number of addresses of the control RAM which are utilized. Apparatus for establishing the correct addressing sequence is described.
A method for providing test vectors adapted to test very large scale integrated circuit devices includes the steps of measuring testability employing a test counting procedure to provide a plurality of test count matrices. Sensitivity values are then enumerated by driving individual sensitivity values forwardly and rearwardly through the circuit, starting at the input terminals, until the test counts are accumulated. The enumerations define test vectors capable of testing the actual circuit. If the circuit includes reconvergent fanout loops, then these loops are enumerated first to provide partial solutions adopted during subsequent global enumeration.
