A storage arrangement is used as an associative memory having a main memory serving to accommodate the data composed of an associative component (association word) and a non-associative component. A comparator device serves to compare the associative part of the read-out data with a search word and address converters serve to derive storage addresses from the association word or the search word or from parts of such words (prefix). An extension counter is provided whose count influences the address derivation and is increased by one whenever an initially addressed storage position proves otherwise engaged. The main memory comprises a linearly addressed storage bank which is divided into a plurality of pages each comprising a plurality of rows. Each row contains one storage position for accommodating the data, and the sections for accommodating reference characteristics. Separate address covers are provided for the formation of the page and row addresses and the extension counter co-determines the derivation of the page address in accordance with its relevant count. A book-keeping memory, which is read out row-by-row comprises a plurality of rows each having a plurality of bit positions. Each row of the book-keeping memory is assigned to a page and each bit position is assigned to a row of the main memory. Seizure of the bit positions of the book-keeping memory provides information on seizure of the main memory and the book-keeping memory is assigned a book-keeping control unit which controls the setting and the interrogation of markings in the book-keeping memory for seized storage positions in the main memory and the selection of equivalent storage positions.
A memory control method and apparatus useful in an input/output buffer memory of a multistation system. The buffer memory storage locations are dynamically divided into a plurality of unit groups having varying storage capacities, and flags are provided which indicate whether or not units are in use. When buffer memory is requested, the size of the requested area is divided by the size of a unit to determine the number of units required and a bit pattern indicating this number is provided. The bit pattern is successively compared and shifted with respect to the flags until the required number of adjacent unused units is found.
A data storage system for storing a number of associations between pairs of data patterns, each including a plurality of data elements and having a plurality of data processing and storing units, and circuits for providing the data patterns to the processing and storing units, each of such units processing and storing information relating to different portions of at least one of the patterns.
Register selection apparatus which includes a plurality of specially mapped programmable memories each addressed by a respective portion of an updatable allocation register which indicates the free and assigned states of a plurality of registers. The resulting memory words read out from the memories are applied to a plurality of multiplexers for identifying a particular predetermined group of registers as being available for assignment. The memory words also provide signals for use in determining whether a sufficient number of free registers are currently available for assignment.
A display apparatus includes a host processor (14) with associated main memory (24) and a display processor with associated display memory (30) and texture memory (41'). The host processor includes an arrangement (18) for storing in the texture memory (41') at least one pyramidal or part-pyramidal array of texel values representing a given texture at at least two levels of resolution defined by respective values of a level coordinate (L) and an arrangement (18) for supplying object primitive data to the display processor (28',49). The display processor includes a processing unit (28') for generating from the object primitive data a series of pixel addresses (X,Y) for application to the display memory (30) and a corresponding series of 2-D texture coordinate pairs (U,V) each with an associated level coordinate (L), to effect a mapping of the stored texture onto the object primitive at a level or levels of resolution defined by the level coordinate (L). The texture memory includes a linearly addressed (one-dimensional) texture memory (41'). The arrangement for storing the pyramidal or part-pyramidal array of texel values includes an arrangement (D1) for storing each 2-D array thereof in linear form in the texture memory (41'). A texture management circuit (49) includes circuitry (50) for receiving and storing page location information (SWI1,W1,B1) for locating each such array in the texture memory. The texture management circuit (49) further includes circuitry (50 to 63) for using the stored page location information to convert the received texture coordinate pair (U,V) and level coordinate (L) into a linear physical texture memory address (A1).
Allocation of space of peripheral storage devices to host processes is based upon free or unallocated space in each such device. The device, irrespective of capacity, having the largest free space is most likely to receive a next space allocation. A central record in a multi-host system stores free space indications. In a disk storage device free space is indicated by the number of unallocated data storage record tracks for each such device.
