A data buffer makes use of a plurality of buffer storage cells into which serial bit streams are sequentially written, in order to obtain correction for phase jitter. A write clock signal is derived from the serial bit stream and is used to sequentially write the digits into the cells. A stable clock source is used to provide the basic timing for sequentially reading the bits out from the buffer storage cells, and a logic circuit is used in conjunction therewith to obtain the retimed serial bit stream. The write and read timing signals should have a maximum time separation to allow for maximum correction of phase jitter, and it is critical that the write and read signals should alternate. A monitor and reset circuit compares a selected write signal with a selected read signal and, where a violation of the alternating write-read condition occurs, the circuit resets the write timing and holds it until the read timing has attained a particular state.
Read and write addresses on the local and line sides of a SONET elastic store are compared at least twice in order to determine any ambiguity in the comparison and, if so determined, foregoing any pointer adjustments that would otherwise have been made.
A jitter resistant clock regenerator for receiving program data transmitted on a transmission channel in synchronism with a transmission clock signal and cancelling jitter, having occurred on the channel, to restore from the transmitted program data a highly accurate program clock signal from which the jitter is removed. The regenerator includes a buffer for temporarily storing transmitted data received over the channel. A read clock selector monitors the buffer to determine the amount of the transmitted data stored in the buffer, and selects one of read clock signals in response to the data amount. A program clock acquisition circuit reads out the transmitted data from the buffer in response to a read clock signal selected by the selector, and restores the clock signal of the program data from the transmitted data.
A digital data transmission system comprises a transmitter and a receiver, said transmitter comprising storage means for temporarily storing a data bit string forming a coded digital video signal, means for supplying a read request signal for reading out said data bit string from said storage means, means for forming one frame out of time slots alloted to a frame synchronization bit, a predetermined number of data bit of said data bit string and a dummy flag bit which indicates whether or not a dummy bit exists in said one frame, means for detecting whether or not a fixed bit pattern is formed in said one frame, means for providing said dummy bit to a predetermined one of said time slots in response to the result of said detection, means for inserting a dummy flag bit indicative of whether or not the dummy bit has been inserted to a time slot for said dummy flag bit, means for supplying a data bit which have dropped out by addition of said dummy bit to said frame forming means so that said dropped data bit is inserted as a part of said data bits forming a succeeding frame, and means for suspending the supply of said read request signal for the bit corresponding to said dropped data bit; said receiver comprising an input terminal for receiving in serial fashion the transmitted data bit string supplied from said transmitter, means for detecting said dummy flag bit in said transmitted data bit string, and means for separating said transmitted data bit string into a dummy bit and input data bits in response to the detection of said dummy flag bit.
Dejitterizer apparatus is disclosed which uses a counter to track the number of bits stored in a 64-bit FIFO buffer. The counter is incremented on a falling edge of pulses of a timing pulse signal, nominally 6.176 Mhz, that coincides with a pulse of a jittered, nominally 1.554 Mhz, clock pulse signal derived from a jittered T1 signal applied to the input of the apparatus. The counter is decremented on the rising edge of pulses of a local clock pulse signal which is derived from the timing pulse signal. The bits are stored in the buffer in response to pulses of the jittered clock pulse signal. Output from the buffer in response to timing pulses derived from the local clock pulse signal is enabled when the counter indicates that the buffer is one-half full. The frequency of the local clock pulse signal is a function of the average frequency of the jittered clock pulse signal over more than sixteen jittered clock periods.
A circuit arrangement for synchronizing source data from a source system with a clock and/or clocks from a sink system. The circuit arrangement includes a source counter, a buffer, a sink counter and a controller. The source data is placed in consecutive buffer positions under the control of the source counter. The sink counter is made to "follow" the source counter and identifies the location in the buffer whereat output data is to be extracted. The controller monitors the counters and generates control signals representative of the state of the buffer.
