Effective expansion of a common intermediate buffer memory by equivalent use of the buffer memory in each CPU in a multiprocessor system. A method and system for achieving buffer memory coincidence is applied to a multiprocessor system provided with central processing units, buffer memories contained in respective central processing units, a main memory, and an intermediate buffer memory connected between the main memory and the buffer memories, wherein a buffer invalidation address information (BIA GO) is sent from the intermediate buffer memory to the i-th central processing unit (BIA GO #i) in accordance with the following logical expression: where the term "REQ.CPU" indicates that the i-th central processing unit does not provide a request for accessing the intermediate buffer memory, the term "W" indicates that the above request is a request for writing a data block, term "F" and "F" indicate that the accessed data block is found and is not found, respectively, in the intermediate buffer memory, the term "COPY #i" indicates that a copy of the corresponding data block is stored in the buffer memory of the i-th central processing unit, the validity flag term VIF indicates the possibility that the copy flags are incorrect, and the symbols "x" and ".upsilon." represent a logical product and a logical sum, respectively. This method makes it possible to store data blocks which exist only in the buffer memory but do not exist in the intermediate buffer memory.

The disclosed embodiments filter out many unnecessary interrogations of the cache directories of processors in a multiprocessor (MP) system, thereby reducing the required size of the buffer invalidation address stack (BIAS) with each associated processor, and increasing the efficiency of each processor by allowing it to access its cache during the machine cycles which in prior MP's had been required for invalidation interrogation. Invalidation interrogation of each remote processor cache directory may be done when each channel or processor generates a store request to a shared main storage. A filter memory is provided with each BIAS in the MP. The filter memory records the cache block address in each invalidation request transferred to its associated BIAS. The filter memory deletes an address when it is deleted from the cache directory and retains the most recent cache access requests. The filter memory may have one or more registers, or be an array. Invalidation interrogation addresses from each remote processor and from local and/or remote channels are received and compared against each valid address recorded in the filter memory. If they compare unequal, the received address is recorded in the filter memory as a valid address, and it is gated into BIAS to perform a cache interrogation. If equal, the inputted address is prevented from entering the filter memory or the BIAS, so that it cannot cause any cache interrogation. Deletion from the filter memory is done when the associated processor fetches a block of data into its cache. Deletion may be of all entries in the filter memory, or of only a valid entry having an address equal to the block fetch address in a fetch address register (FAR). Deletion may be done by resetting a valid bit with each entry.

In a system including a single main storage or memory and two or more processing units sharing the main storage or memory, there are provided two address arrays for storing the addresses of the data of the main storage or memory which is stored in a buffer storage or memory, one address array storing the same addresses as those stored in the other address array. One of the address arrays is used for reference to the buffer storage or memory by the own or associated processing unit, while its other address array is used for detecting that the store address from another processing unit to the main storage or memory is coincident with one of the addresses stored therein. When the coincidence of addresses is detected, the corresponding address in the other address array is invalidated or cancelled, and the roles of the two address arrays are interchanged. Subsequently, the corresponding address in the one address array is invalidated cancelled. During this period of time, the reference for the own or associated processing unit is performed by its other address arrays without interruption.

In a lock control for a shared storage, each storage controller (SC) includes circuitry (LKA) for holding the addresses locked by any of the storage utilizing units connected thereto and circuitry (FLKA) for holding a copy of the contents of LKAs of the other SCs. When one storage utilizing unit connected to one SC issues a storage access request, its requested address is compared with the contents of the LKA and FLKA in the associated SC, thus determining whether or not the requested address is locked by any other storage utilizing unit connected to that particular SC or by any of the storage utilizing units connected to the other SCs. Each storage utilizing unit may include a FLKA.

A storage control system controls the update operations on two buffer address arrays in a data processing system in which a plurality of processors are connected to a shared storage, at least one of the processors having a buffer storage. The first buffer address array is the directory of buffer storage. The second buffer address array contains the same data as that of the first buffer address array. The storage control system updates first the content of the second buffer address array then that of the first buffer address array in response to a block transfer to the buffer storage of the own processor and a store operation conducted by other processor on the shared storage. The storage control system permits to accept a new access request occurred in the own processor on condition that a block transfer to the own processor is finished and that the first buffer address array is updated in association with the block transfer.