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Solid-state delay timed switching circuit
   
Document Number
US Patent 4062007
Issued Date
December 6, 1977
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Abstract
A solid-state delay timed switching circuit includes a delay timing means for delaying the start of an operational sequence. A function timing means is provided for timing the operational sequence, an alarm timing means for timing an audible alarm at the completion of an operational sequence, a power switching means, a power supply and a power turn-off means to de-energize the power switching means.
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Solid-state delay timed switching circuit - US Patent 4062007 Drawing
Drawing from US Patent 4062007
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Number of Claims:
11
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Owner
P. R. Mallory & Co. Inc. (Indianapolis, IN)
Published
December 6, 1977
Application Number
05/724,346
Filed
September 17, 1976
US Classification
340/309.9   307/141 340/309.4
Int'l Classification
H03K   17/28   (20060101)   H03K   17/292   (20060101)  
Examiner
Attorney/Law Firm
USPTO Field of Search
307/141   340/309.1   340/309.4  
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