A level sensitive scan design (LSSD) Latch Cell that is adaptable to very large scale integrated (VLSI) Semiconductor circuit fabrication is disclosed. The Latch Cell includes a static functional latch and a dynamic test latch, both of which are controlled by a data selector that selects input data from either a functional data source or test data from another test latch in a scan data path.

A logic circuit on a substrate is switchable between a test mode and an operational mode. First and second NOR gates are cross-coupled and may be switched between an operational mode and a test mode by the application of a control signal to first and second transfer gates coupled to the inputs of the NOR gates. The first NOR gate includes a p-type region and an n-type region formed in said substrate and traversed with first and second conductive layers insulated from the p and n-type regions. Thus, the first NOR gate includes two p-channel transistors and two n-channel transistors. The second NOR gate is also formed by a p-type region and an n-type region traversed with third and fourth conductive layers. Thus, the second NOR gate also includes two p-channel transistors and two n-channel transistors. The transfer gates are located on the substrate between the first and second NOR gates. Both transfer gates include an n-type region formed in the substrate with a conductive layer disposed over the n-type region. In the operational mode, the cross-coupled NOR gates may perform as a flip-flop. In the test mode, each NOR gate essentially becomes an inverter.

The present invention can include a method and system for testing IC chips, including the steps of performing a binary search to a first failing pattern, determining a failing sink latch, performing a back cone trace to determine all source latches, determining source latch logic states, positioning the source latch logic states in a scan chain, exercising a chip scan path by applying logic transitions on the source latches in the absence of a system L1 clock, and observing an exercised failing circuit. The invention can include the use of PICA techniques to observe the exercised failing circuit. In another embodiment, the invention can include using LBIST or a WRP technique to search for the failing pattern. In yet another it includes the step of using an algorithm to exercise the exercised failing circuit. In another embodiment, the method includes the step of creating a net pattern to be scanned including a sum of an original pattern causing a failing circuit to be exercised, and one or more shifted versions of the original pattern. The algorithm can include a step where one of the shifted versions is shifted a number of clocks wherein the number of clocks is equal to the length of the original pattern. In one embodiment, one of the shifted versions is shifted a number of clocks, wherein the number of clocks is chosen so that the sum of the original pattern and the one of the shifted versions does not cause a scan conflict. In another embodiment the method further includes the step of using an algorithm to densify the pattern set.

The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.

The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.