 |
Claims  |
|
|
I claim:
1. A multiplexing machine control communications system for controlling a
plurality of machines from a programmable controller, comprising
a multiplexer controller terminal for receiving condition-defining
information signals representing the operational functions of a plurality
of independently operable multifunctioning machines and transmitting
predetermined command signals to control selected functions of each of
said machines,
a programmable controller coupled to said multiplexer controller terminal
to provide a source of said predetermined command signals for controlling
said machines in response to said condition-defining information signals,
a plurality of multiplexer machine terminals, one coupled to each one of
said plurality of independently operable multifunctioning machines to
transmit condition-defining information signals responsive to the
operational functions of a machine coupled thereto and to receive in
response thereto selected ones of said predetermined command signals,
an input and output converter coupled between said multiplexer machine
terminal and a machine coupled thereto for coupling said information and
command signals therbetween,
respective transmission lines for connecting said multiplexer controller
terminal in parallel with each of said multiplexer machine terminals,
said multiplexer machine terminals operating independently of each other
for communication between said multiplexer controller terminal and each of
said multiplexer machine terminals, and
safety circuit means for monitoring the transmission of data on said
transmission lines and providing inhibit signals for inhibiting data
transfer within the system when transmission on said lines is interrupted.
2. A system as in claim 1 including time delay means in said machine
terminal for providing time delay at turn on of the said machine terminal
for assuring that the machine terminal is in synchronism with the
controller terminal before data is processed by the machine terminal.
3. A system as in claim 2 wherein said time delay means includes
a capacitor which begins to charge when the system is turned on and reaches
a preset level of charge at a predetermined time after turn on,
gating devices connected to said capacitor for controlling the transfer of
data through associated machine terminals,
said gating devices having distinct operating states responsive to the
charge on said capacitor, and
said gating devices being shifted to an operating state for allowing data
to pass therethrough only after said capacitor is charged to said preset
level.
4. A system as in claim 1 wherein said safety circuit includes
capacitor storage means coupled to said transmission lines to be charged
thereby during transmission of data signals,
means coupling said capacitor storage means to said transmission lines for
discharging said capacitor storage means upon termination of data
transmission, and
gate means coupled to said capacitor storage means for selectively gating
the transmission of data signals through said transmission lines in
response to the charge on said capacitor storage means.
5. A system as in claim 1 wherein said safety circuit includes
capacitor storage means for storing a charge in response to the
transmission of data through said transmission lines,
means for discharging said capacitor storage means upon the interruption of
transmission of data through said transmission lines,
gate means having first and second operating states connected to said
capacitor means for selectively enabling the inhibiting transmission of
data through said transmission lines in response to the level of charge on
said capacitor storage means,
said first operating state of said gate means gating the transmission of
data to and from said transmission lines, and
said second operating state of said gate means inhibiting the transmission
of data to and from said transmission lines.
6. A system as in claim 4 wherein said safety circuit further includes
manual reset means for manually controlling the resumption of operation of
said system coupled to said gate means to enable the re-establishing of
data transmission through said transmission lines upon the charging of
said capacitor storage means to a predetermined level.
7. A system as in claim 4 wherein said safety circuits include shift
register means coupled to said capacitor storage means, and
said shift register means being resettable in response to continuing data
input through said transmission lines to the associated terminal for
maintaining a predetermined charge on said capacitor storage means
sufficient to enable continuous transfer of data.
8. A system as in claim 4 further including time delay means in said
multiplexer machine terminal for providing time delay at turn on of said
machine terminal for assuring that the machine terminal is in synchronism
with the controller terminal before data is processed by the machine
terminal, and
manual reset means for manually controlling the resumption of operation of
said system coupled to said gate means to enable the re-establishing of
data transmission through said transmission lines upon the charging of
said capacitor storage means to a predetermined level to control the state
of said gate means to re-establish data transmission through said
transmission lines.
9. A system as in claim 2 wherein said safety circuit means includes
capacitor storage means coupled to said transmission lines to be charged
thereby during transmission of data signals,
means coupling said capacitor storage means to said transmission lines for
discharging said capacitor storage means upon termination of data
transmission, and
gate means coupled to said capacitor storage means for selectively gating
the transmission of data signals through said transmission lines in
response to the charge of said capacitor storage means.
10. A system as in claim 9 further including manual reset means for
manually controlling the resumption of operation of said system coupled to
said gate means to enable the re-establishing of data transmission through
said transmission lines upon the changing of said capacitor storage means
to a predetermined level to control the state of said gate means to
re-establish data transmission through said transmission lines.
11. A machine control communication system for controlling a plurality of
machines from a programmable controller operating with a scan cycle of a
plurality of distinct periods, comprising
a multiplexer controller terminal for receiving condition-defining
information signals representing the operational functions of a plurality
of independently operable multifunctioning machines and for transmitting
predetermined command signals to control selected functions of each of
said machines,
a programmable controller coupled to said multiplexer controller terminal
to provide a source of said predetermined command signals for controlling
said machine functions in response to said condition-defining information
signals,
a plurality of multiplexer machine terminals, one coupled to each one of
said plurality of independently operable multifunctioning machines to
transmit condition-defining information signals responsive to the
operational functions of a machine coupled thereto and to receive selected
ones of said predetermined command signals,
an input and output converter coupled between each multiplexer machine
terminal and a machine coupled thereto for coupling said information and
command signals therebetween,
transmission lines connecting said multiplexer controller terminal with
each of said multiplexer machine terminals for enabling communication
between said multiplexer controller terminal and each of the multiplexer
machine terminals,
a dependent multiplexer machine terminal serially connected with one of
said multiplexer machine terminals to said multiplexer controller
terminal,
said dependent multiplexer machine terminal being operable in series with
said one multiplexer machine terminal, and
switch means for controlling the transmission and receipt of said signals
from said one multiplexer machine terminal positionable to determine which
of said serially connected multiplexer machine terminals is to operate
during a given period of the scan cycle.
12. A communication system as in claim 11 wherein said switch means
comprises a plurality of input lines each selectively receiving enabling
signals during a given period of each scan cycle and an equal number of
output lines for coupling signals therebetween,
a plurality of switches for coupling each inout line to a respective one of
said output lines to couple said enabling signals thereto,
gate means connected to said output lines for coupling the output signals
thereon as a single output signal from said gate means,
first and second logic circuit means respectively associated with said one
and said dependent machine terminals and coupled to said gate means to be
selectively energized thereby, and
said first and second logic circuit means being selectively energized
during a selected period of said scan cycle by said output signal from
said gate means when transmitting data from said multiplexer machine
terminal asociated therewith.
13. A communication system as in claim 11 wherein said switch means
comprises a switch assembly including a plurality of individual switches,
each of said switches being connected in the operating circuit and
sequentially actuable during a particular period of each scan cycle.
14. A communication system as in claim 13 wherein the closure of an
individual switch couples a succeeding dependent multiplexer machine
terminal to enable transmission from said succeeding dependent terminal
and disconnects the preceding multiplexer control terminals.
15. A communications system as in claim 13 including means for selectively
addressing incoming data to each multiplexer terminal and the selection of
transmission from a particular multiplexer machine terminal in a series is
determined by the position of the respective individual switch associated
with the selected period of the scan cycle.
16. A communication system as in claim 13 wherein said switch assembly is
connected to a decoder which establishes the period of the scan cycle
wherein information is transmitted by a dependent multiplexer machine
terminal.
17. A communication system and as in claim 13 wherein the individual
switches defining each transmission period of the scan cycle are closed
when a succeeding multiplexer machine terminal is to transmit information
and wherein said individual switches are open when the multiplexer machine
terminal in which said switch means are located is to transmit data.
18. A communication system and as in claim 17 wherein individual
transmission periods are varied dependent on said switch means. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
BACKGROUND OF THE INVENTION
This invention relates in general to machine operation control systems and,
more specifically, to a method of and apparatus for monitoring and
controlling the operation of preselected functions of individual machines
in a plurality of machines.
More particularly, this invention relates to a digital communications
system wherein specific operational functions of each machine in a series
of machines are monitored and controlled from a single control subsystem
or controller to assure individual machine performance in accordance with
a predetermined program.
In all manufacturing and production operations, it is necessary to monitor
and control the operation of the equipment used in the production and
manufacturing processes. In certain applications this monitoring and
controlling function is performed by the individual machine operator who
may control more than one machine, depending upon the number of operations
which must be monitored, and the frequency with which changes occur in
these conditions and operations. However, the capabilities of an
individual machine operator to control and monitor the equipment which is
being utilized are limited. Therefore, it has been attempted to monitor
the operation of these machines and to control their functioning through
the use of a predetermined control program which monitors the various
functions and conditions of a machine and controls the operation of the
machine in response to these monitored conditions to insure satisfactory
operation.
One attempt to provide such a solution to this problem has been the use of
a controller which is programmed to couple predetermined control or
command signals to the machines in the event a predetermined condition is
detected thereby causing the command or control signal to be generated. In
certain of these applications the detector or sensor which monitors the
condition or operation, and the programmer or controller which generates
the responding command signal, are each electrically coupled one to the
other by wire pairs. This coupling or hard wiring necessitates a
substantial expenditure of money for labor costs as well as the materials
utilized in hard wiring the machine to the controller. Such a system
obviously requires a controller to be in close proximity to the machine
from a physical standpoint due to the large number of wire pair
connections which must be made between the units.
Another attempt to provide a satisfactory solution to this problem has been
the use of various multiplexing systems using a common transmission line
or signal carrier between the machine and the controller wherein each of
the individual functions of the machine which are monitored and the
responding control signal generated to control proper machine operation
are all transmitted by the common signal carrier. Such systems overcome
the difficulties associated with hard wiring each monitor or sensor to its
respective controller since they utilize a common transmission line, but
they are limited as to the number of conditions which can be monitored
within a given time frame.
In such a system each of the functions is sequentially monitored and the
corresponding control signal coupled to the sensor. Such a system not only
controls changes in the state of the sensed condition in response to the
programmed control, but also insures that the correct state is maintained.
These systems address each sensor and generate a command or control signal
to the machine at every address regardless of a change of state in the
controlled function or operation. Such a redundant system is satisfactory
in applications where the number of monitored conditions is such that the
entire system may be monitored or addressed within the limits of a
predetermined maximum time frame. However, such systems are not
satisfactory for use in monitoring a large number of inputs, or in smaller
systems wherein the maximum time period within which a condition must be
monitored or addressed is less than the time period required for the
multiplexing system to complete its entire address cycle monitoring all
terminals. In such systems if a monitored function were to change state
immediately after the sensor has been addressed, the condition could not
be changed until the next cycle -- after all of the other machine
functions or operations had been addressed and the corresponding command
signal transmitted to each receptor. In many applications such a time or
cycle period is too great.
In monitoring or controlling machine operations where the "redundant" type
of multiplexing systems, such as previously discussed, are not suitable
due to the cycle time delay inherent in this system, a priority system has
been utilized. In such systems the functions or conditions are arranged in
priority of importance and sequentially addressed in synchronism, but no
command signal is transmitted unless a change of state has been detected.
The individual sensors or detectors of each group are addressed, and, upon
a change being detected, a command signal is generated to correct or
change the condition or function. At the end of the transmission cycle to
that particular receptor, the entire functions or controls series are
again addressed beginning with the highest priority function or control,
and the addressing of the entire cycle restarted to continue until a
change is detected. Such a system requires that each of the functions or
controls which are to be monitored must be ranked according to their
importance, and presents the problem that the lower ranked priorities may
never be monitored.
In another type of priority system the monitored functions or controls are
electrically coupled into two groups. The first group comprises a small
number of high priority terminals and the second group contains the
remaining monitored terminals. The high priority group is sequentially
addressed and a command signal is generated for each of the functions in
this group in the manner previously described with reference to the
"redundant" type of multiplexing system. The remaining functions or
controls are addressed, but no command signal is generated unless the
sensor for these controls or functions has indicated that a change or a
command signal is necessary.
Another type of priority multiplexing system utilizes a random access
memory and a two-speed addressing rate which addresses all of the
monitored conditions to determine a change of state requiring a response,
but only transmits data through the common signal carrier upon the
occurrence of a monitored event or the sensing that a response-requiring
change has occured. While this system eliminates the problems incurred by
delay time due to the transmission of command signals to functions or
controls which do not need a command signal for proper operation, they
require further and more sophisticated electronics in that the individual
monitors or detectors must be provided with additional informational data
identifying the receptor to insure correct correspondence between the
function monitored and the command signal generated in response since
there cannot be any synchronization between the controller and the
receiver. The resulting random transmission of control or command signals
to the monitored receptors must, therefore, be accompanied by
informational data which correlates the particular function or control
which is being monitored and the command signal directed to change the
state of a particular operation or function to insure that the command
signal is coupled to the appropriate receptor. Such a system requires
highly sophisticated electronics and is, therefore, expensive.
With all of the various types of priority systems which have been utilized,
each of these systems is burdened with the inherent problem that, in order
to give certain machine functions priority, other monitored functions must
of necessity yield to these priorities. Therefore, the secondary or
non-priority functions may become critical through lack of a command
response being directed to the receiver because of the continued
utilization of the common signal carrier or transmission line by the
higher priority informational data. Even though the various multiplexing
systems discussed above are of benefit in minimizing the expenses incurred
in monitoring and controlling the operations of a machine, such systems
inherently present further problems which must be minimized in order to
obtain an economical and commercially acceptable system.
BRIEF SUMMARY OF THE INVENTION
It is therefore, an object of this invention to improve systems for
monitoring and controlling the operation of production machinery.
It is another object of this invention to monitor the operational
functioning and controls of a machine and to control its operation in
accordance with a predetermined program.
A further object of this invention is to monitor and control the
operational functions of individual machines through a programmable
controller used to control the operations of a plurality of machines.
Still another object of this invention is to control multiple operations
and functions of machinery through a controller coupled to the various
monitoring stations by a common signal carrier.
Yet another object of this invention is to minimize hard wiring between
programmably controlled machinery and the programmed controller by
utilizing a common signal carrier.
These and other objects are attained in accordance with the present
invention wherein there is provided an information directing system
coupling condition-defining signals generated by monitoring the operation
of each of a series of multi-functioning machines to a programmable
controller wherein each of the monitored operations is controlled in
accordance with a preselected program. The system monitors and controls
individual machine operations of a series of machines by means of the
preprogrammed command signals generated to control the monitored
operations and couples the various condition-defining signals and
responding command signals through a common signal carrier or transmission
line.
Basically, the system comprises a controller-machine combination involving
a programmable controller having groups of output lines which carry the
machine command signals as updated by information obtained from the
machines, and groups of input lines to which the corresponding information
from the machine is routed so as to update the controller. A multiplexing
transmitter/receiver assembly connected to the input and output lines of
the controller and driven by a free-running clock simultaneously transmits
the command signals information in multiplexed format and receives the
groups of machine information for demultiplexed routing to the appropriate
groups of controller input lines. A similar multiplexing
transmitter/receiver assembly is connected to the machine and is likewise
driven by a free-running clock simultaneously to receive/demultiplex the
transmitted command signals for appropriate application to the machine
controls and to transmit the machine data in multiplexed format back to
the controller-associated assembly. Each transmission cycle is
characterized by the successive transmission of the individual groups of
command or machine-information signals, followed by a "dead" time
whereafter the cycle repeats. The machine-associated receiver utilizes
this "dead" time not only to maintain its transmitter and receiver in
synchronism but also to slave/synchronize the machine assembly to the
controller assembly despite the fact that each is driven by a separate
free-running clock system. The transmission from the two assemblies of
each controller/machine combination occur concurrently but it is the
transmission from the controller-associated assembly which controls the
system because the event marked by the ending of its transmission cycle is
that which is employed to control or synchronize the machine-associated
assembly.
Further objects of this invention, together with additional features
contributing thereto and advantages accruing therefrom will become
apparent from the following detailed description of one embodiment of the
present invention when read in conjunction with the accompanying drawings,
wherein:
FIG. 1 is a block diagram of a machine control system which may be
constructed according to this invention;
FIG. 2 is a block diagram illustrating certain principles of each basic
controller/machine system;
FIG. 3 is a circuit diagram illustrating a machine multiplexer terminal;
FIG. 4 is a circuit diagram of a machine-associated transmitter multiplexer
matrix;
FIG. 5 is a circuit diagram of a machine-associated receiver receiver
demultiplexer matrix;
FIG. 6 is a circuit diagram illustrating a unit in the controller
multiplexer terminal;
FIG. 7 is a circuit diagram of a controller-associated receiver
demultiplexer matrix;
FIG. 8 is a circuit diagram of a controller-associated transmitter
multiplexer matrix; and
FIG. 9 is a block diagram illustrating the principle of machine serializing
.
DETAILED DESCRIPTION
As is well known, certain operation characteristics of machinery are
capable of being determined through the use of, for example,
microswitches, limit switches, photo-sensors, or other suitable condition
responsive devices. These operating functions or characteristics indicate
normal operation as well as malfunctions of the machine, and in many
instances the operations are interdependent such that a change in one
operation requires a coordinate response in another operation to insure
continuous satisfactory production.
There is in the logic block diagram a plurality of multi-functioning
machines, M1 - MX individually coupled to a centrally located programming
controller 12, by means of transmission lines T1-T8. The programmable
controller 12 is programmed with a program compatible with the
controller's programming panel to control a number of machines or
processes. Since the speed of operation of the controller is so much
faster than that of the parallel coupled machines, the controller can
communicate with and thus operate one or more of the machines concurrently
and essentially independent of the other machines. The programming
controller 12 receives the information from various sensors in each of the
machines, the information is correlated by the controller and data in
response to the information from the sensors is coupled to each of the
individual machines to control its operation. The controller 12 is a
solid-state modularized system designed to control operations or processes
that can be logically arranged into a number of discrete steps of logical
expressions, each with just two states; i.e., status inputs are either on
or off, and the control operation selects outputs and turns them on or
off. This type of control sequence is used in mass-production equipment
and materials handling systems as found in such varied industries as
automotive, steel and food processing and is commercially available as
Model DEC 14/30 Industrial Control System Model 14/30 manufactured by the
Digital Equipment Corporation, Maynard, Mass. The DEC 14/30 System uses a
replaceable memory to direct specific control operations. Convenient
computer programming techniques allow the user to design a memory to suit
his unique control needs, and the entire control process can be redefined
by changing the memory.
The DEC 14/30 System is designed to operate independently or with computer
monitoring or control. Since the DEC 14/30 can access all control inputs
and outputs, the monitoring components may be a general purpose computer
and a suitable interface device. Further, a group of DEC 14/30 Systems can
be monitored by a single computer using a multiplexer to provide status
and malfunction reports for a large control complex.
As shown in FIG. 1, controller 12 provides a multitude of
condition-responsive command signals through a multiplexer controller
terminal 15 and the transmission lines labeled T1, T2 - T8 to respective
Multiplexer Machine Terminals MT1, MT2 - MTX. Each of the Multiplexer
Machine Terminals MT1, MT2 - MTX is coupled to respective input and output
converters labeled I01, I02 - I0X to respective machines M1, M2 - MX.
Conversely, the Multiplexer Machine Terminals MT1, MT2 - MTX couples a
multitude of condition-defining information signal outputs indicative of
the respective machine M1, M2 - MX through transmission lines T1, T2 - T8
to the Controller terminal 15. More specifically, and as will be explained
further hereinbelow, when a machine, for example, Machine M1, changes its
status or position, converter I01 converts the new status or position
information to logic level data which Multiplexer Machine Terminal M1
translates to binary data which is coupled back through transmission line
T1 and controller terminal 15 to the controller 12. Controller 12 compares
this new machine data with the pertinent programmed or control information
to continue the operation in progress, to initiate a new operation as
required, or change the operation.
The basic operation of the system is illustrated in FIG. 2 which
diagrammatically illustrates one multiplexer machine terminal system MTN
and the corresponding portion of the multiplexer controller terminal
system 15. The two systems include the respective free-running clocks A
and A', which drive the receiver demultiplexer sequencers B and B' and the
transmitter multiplexing sequencers C and C' at a relatively slow byte
rate while driving the respective UAR/T transmitters 74 and 74' and the
UAR/T receivers 74A and 74A' at a relatively rapid rate. The units 74 and
74' (and also 74A and 74A') contain internal divide-by-sixteen counters so
that the bit rate of the system is one-sixteenth that provided by the
inputs of the clocks to these units. The transmitters 74 and 74' accept
parallel bit inputs and transmit them serially, together with start, stop
and parity bits to the receivers 74A and 74A' respectively, whereas the
receivers accept the serialized bytes and output them in parallel. The
demultiplexers D and D', under control of the sequencers B and B'
sequentially step the byte information to the groups of controlled devices
F1 - FN and to the controller over the input lines G1 - GN. Dependent
upon the controller program as influenced by the inputs at G1 - GN, the
controller outputs the command signals at the lines H1 - HN. These
commands are multiplexed by the multiplexer I, serialized by the
transmitter 74', received by the receiver 74A and provided as parallel
outputs thereby to the demultiplexer D where they are sequenced to the
appropriate groups of controlled devices F1 - FN. The groups of sensors K1
- KN monitor the corresponding controlled devices F1 - FN and provide the
inputs to the multiplexer I' which are applied in sequence to the
transmitter 74, serialized thereby, and which ultimately appear as the
updating data at the controller input lines G1 - GN.
The two sequencers B and C are controlled by an end-of-transmission
detector L to be reset simultaneously thereby. The sequencers operate, in
principle, as if there are N+1 states, N being the number of the groups F1
- FN or groups K1 - KN, etc., with there being only N transmissions (and
corresponding receptions) per cycle. In this way, there is a "dead" byte
period separating successive cycles which is used to detect
end-of-transmission by the controller assembly. Since the two sequencers A
and C are reset simultaneously, they remain synchronized so that each
cycle starts with the reception of the first group of command signals
applicable to the controlled device group F1 and the transmission of the
first group of data signals from the sensor group K1. The detector L
effectively slaves each machine terminal system to the controller terminal
system and allows all of the clocks to be free-running. The only
constraint on the clocks is that they all be sufficiently accurate as to
avoid such gross misphasing during any one cycle as would defeat the
effect of the slave-inducing detector L.
FIG. 1 illustrates a possible arrangement of controlled machines. The
controller 12 is connected to the multiplexer controller terminal 15 which
comprises eight of the transmitter/receiver systems illustrated at the
left-hand side of FIG. 2 connected respectively to the multiplexer machine
terminals MT1 - MT8 each of which comprises a transmitter/receiver system
as illustrated at the right-hand side of FIG. 2. Each group of sensors K1
- KN and controlled devices F1 - FN is associated with a corresponding
machine M1 - M8 and are interfaced therewith by means of the input and
output converters IO1 - IO8. Additionally, there are the two multiplexer
machine terminals MT9 and MTX serially connected from the terminal MT8, as
detailed hereinafter, and their corresponding input and output converters
IO9 and IOX and machines M9 and MX.
One of the Multiplexer Machine Terminals is shown in FIG. 3 and comprises a
transmitter section and a receiving section. The transmitter section
includes a clock 61, which is of any suitable known design and includes 1
MHZ oscillator 62, a 4-bit binary counter 63 and a NAND buffer gate 64.
The counter 63 divides the 1 MHZ output from the clock 62 by two, four,
eight or sixteen. In the embodiment shown, a jumper wire 65 is connected
to counter 63 to divide by two and provide a 500 KHZ output. The clock 61
provides clock or timing pulses for the system, and particularly, to the
units labeled UAR/T 74 and UAR/T 74A, as is well known in the art (units
UAR/T 74A will be described hereinbelow).
The output from the clock 61 is coupled through lead 66 to another 4-bit
binary counter 67, connected to divide by 16, and a divide-by-12 counter
69. The oscillator 62 and counters 63, 67 and 69 comprise the clock A of
FIG. 2, the output of the counter 69 being the byte rate clock output of
that Figure. The output from counter 69 is coupled through a monostable
multivibrator 70 and lead 68 to provide pulses to another 4-bit binary
counter 71 which is the sequencer B of FIG. 2, to the NAND buffer gate 73
and to the multivibrator 152 for purposes to be hereinafter explained.
The counter or sequencer 71 is connected to provide a 4-bit binary output
to a binary-to-decimal decoder 72. The decoder 72 is arranged to provide
an output for the first 9 of the sixteen available states of the counter
71, the sequencer being then reset and the cycle repeats. To illustrate,
assuming the sequencer 71 initially to be set to its initial state, output
E1 will be low correspondingly to control the multiplexer matrix (I' of
FIG. 2) as hereinafter described and each of the outputs E2 - E9I will be
high. The gate 73 is thus enabled and the input from the inverter 151 will
be low to the multivibrator 152. A positive byte rate clock pulse at the
line 68 will thus provide an inverted pulse output from the gate 63, the
leading edge of which will cause the transmitter 74 to latch the parallel
input signals at D1 - D8, as dictated by the multiplexer matrix, and the
trailing edge of this pulse will initiate serialization of these signals
from the unit 74. At the same time, the trailing edge of the clock pulse
on line 68 will cause the counter 71 to increment, returning E1 to its
normal high state and causing E2 to go low correspondingly to index the
multiplexer matrix. This sequence continues, driving the lines E3 - E8
successively low. The eighth byte rate clock pulse on the line 68 will
initiate transmission of the eighth byte and will also drive the line E9I
low, thus disabling the gate 73. The low state of the line E9I also
enables the multivibrator 152 by providing a high input thereto through
the inverter 151. The multivibrator 152 will produce an output pulse only
when both inputs thereto are high with one of them negative-going. Thus,
the multivibrator 152 will produce an output pulse at the trailing edge of
the ninth byte rate pulse at line 68 and this will condition the gate 141
so that a coincidental reset pulse on the line 128 (as hereinafter
described) will produce a negative pulse output from the gate 141 which,
inverted by the gate 143 will reset the counter 71 to its initial state in
which only the line E1 is low and the line E9I returns to its normal high
state. Thus, it will be seen that every ninth byte rate pulse will be
blocked by the gate 73 to provide a byte period "dead" time between
successive cycles. It will also be noted that the reset signal on the line
128 also resets the counters 67 and 69 so as to synchronize the sequencer
71 with the receiver 74A from whence this reset signal is initiated and
with the receiver sequencer 90 which is simultaneously reset. The delay or
idle time corresponding to the ninth state of the decoder 72 is used as a
marker for identifying and synchronizing the initiation of the scan
cycles, as will be explained.
The transmitter/receiver units 74, 74A and 74', 74A' are one package solid
state Universal Asynchronous Receiver/Transmitter devices (hereinafter
also referred to as UAR/T) manufactured by General Instrument Corporation,
Micro Electronics Division, 600 West John Street, Hicksville, New York,
11802. Each UAR/T unit includes a receiver section 74A or 74A' which
accepts asynchronous serialized characters and converts them to a parallel
format. Each UAR/T unit also includes a transmitter section 74 or 74'
which independently accepts parallel binary characters and converts them
to a serial asynchronous output with start, stop and parity bits added.
The UAR/T is relatively versatile with the baud rate, bits per character,
parity mode, and number of stop bits being externally selectable, and the
unit will internally synchronize the start bits with the clock input. In
the embodiment shown, the UAR/T units process eight data bits, a parity
bit and the start and stop bits. It should be noted that the data
transmission rate capability of the UAR/T is quite high as compared to the
relatively low operating speed of machines M1 etc. The UAR/T has the
capability of transmitting approximately 40,000 baud or 4000 eight bit
transmissions per second.
As mentioned above, the counter 71 and the binary-to-decimal decoder 72
generate the group-select address pulse. The decoder 72 transforms the
binary output of counter 71 into one of eight mutually exclusive
group-select pulses which is coupled to terminals E1 - E8 to provide a
group-select address. The terminals or leads E1 - E8 are coupled to the
like numbered terminals in FIG. 4 to apply the sequentially selected one
out of eight groups of data bits which is applied to the UAR/T transmitter
section 74.
When a strobe pulse is applied to the transmitter 74, strobing of eight
bits enabled by the decoder 72 occurs. A clock pulse from dividers 67 and
69 and the multi-vibrator 70 is coupled through NAND gate 73 to UAR/T 74
to function as a strobe pulse.
With the beginning of a strobe pulse applied to UAR/T 74, the strobing of
eight bits selected by the decoder 72 occurs. The trailing edge of the
strobe pulse will cause the bits in the particular group to be serially
coupled out of the transmitter 74 through the line driver 75 and the
transmission line.
The data bits D1 - D8 are coupled to UAR/T transmission section 74 in
parallel and are transmitted through the transmission line in serial
fashion as will now be discussed. FIG. 4 shows the multiplexer circuit
assembly or matrix 77 for entering the data bits in parallel to the
section 74. Circuit assembly 77 comprises eight identical switching
circuits labeled G1A-G1B through G8A-G8B, each circuit including two
buffer gates labeled generally A and B, which gates are enabled or
inhibited by the respective enabling lines labeled E1 - E8. In FIG. 4 for
simplicity in the drawing, only four of the eight identical circuits are
shown with the associated buffer gates. The enable lines E1 - E8 will be
driven low or enabled in a sequence from 1 through 8 as the decoder 72
(FIG. 3) is incremented. The enabling lines numbered E1 - E8 are connected
to the similarly numbered terminals of the decimal decoder 72 of FIG. 3.
As mentioned, decoder 72 selects and sequentially couples each of the
mutually exclusive groups of eight bits through matrix 77 to the UAR/T
transmitter section 74. Thus, one of the eight lines E1 - E8 is enabled
during a given period and the remaining lines remain disabled. For
example, when enable line E1 is low, the eight input lines or leads IS1,
IS2 - IS8, which are connected to the input side of the two buffer gates
G1A and G1B, are effectively coupled through the matrix 77 to the output
lines D1 - D8. Output lines D1 - D8 couple the bits in parallel to the
similarly numbered terminals of the UAR/T transmitter section 74 of FIG.
3.
The input leads IS1 - IS8 are connected to respective converters which will
convert a relatively high 60 HZ voltage to selected logic levels. As is
well known, such could be obtained, for example, by means of either a
transformer or photo-optic system whereby a switch opening or closing in a
60 HZ line would be converted through a suitable component, such as a D.C.
bridge, to a distinct logic level. The foregoing would provide
condition-defining binary data information or signals to the circuitry of
FIGS. 3 and 4 relating to the occurrence of an event in the associated
machine. These condition-defining information signals received from the
machine are converted through the Input/Output Converters IO1 - IO9 and
coupled as parallel bits (D1 - D8) to the transmitter section 74. The
UAR/T section 74 serializes the data bits and then couples the data
through the line driver 75 and the transmission line T1 to the Controller
Multiplexer Terminal 15.
The receiver section of FIG. 3 provides a means of receiving
condition-responsive command signals from the Multiplexer Controller
Terminal 15 through the respective associated transmission lines T1 - T8
and couples or conveys this information through the associated
input/output converter IO1 - IO9 to the respective machine M1 - M9 to
affect its operation.
Serialized data from the Controller Terminal 15 is received from the
transmission lines T1 through input gating and shaping circuits 83 and 84
which reshape and square the data bit pulses before they are coupled to
the input of the UAR/T receiver 74A. The receiver 74A restructures the
serialized data D9 - D16 into an eight bit output (D9 - D16) having a
parallel format and the parallel eight bits are coupled out through two
Quad-input AND gates 85 and 86.
Concurrently, the designation as to where each particular group of eight
bits is to be delivered is controlled by one of the eight outputs of a
binary to decimal decoder 72A; decoder 72A being similar to decoder 72. At
the beginning of each cycle, the multiplexer controller terminal commences
transmission of the eight successive bytes which contain the command
signals from the controller 12. At the end of each byte, a high signal is
produced on the output terminal 89 of the receiver 74A. This signal is
used either to increment or to reset the address counter or sequencer 90
as explained hereinafter, and to provide an input to the decoder 72A.
Strobe pulses from the decimal decoder 72A determine which one of the
eight output lines E9 - E16 will go low and strobe the group of eight bits
received by the receiver 74A. The decimal decoder 72A thus determines
where each group of eight data bits applied to the receiver 74A and
available at the output of AND gates 85 and 86 will be coupled to the
machine. The demultiplexer matrix 80 is illustrated in FIG. 5 and its
operation will be evident due to its similarity to FIG. 4.
Returning to FIG. 3, the end of a byte is signalled by a high signal at the
output line 89 and this signal toggles the multivibrator 91 connected to
operate as a flip-flop having a Q output to the gate 130 and a Q output to
the gate 128. The Q output is also connected to the receiver 74A to reset
the internal flip-flop which produced the high signal at the line 89. The
two NOR gates 130 and 131 are cross-coupled as shown and when the Q output
from the device 91 goes high, the normally low output of the gate 131 goes
high and will remain so until the two counters 135 and 134 provide a clock
pulse input to the gate 131. Normally, the counters 134 and 135 are held
reset by virtue of the normally high output from the inverter 132. When
the counters 134 and 135 have counted exactly thirty-two pulses from the
counter 63, an input will be provided to the gate 131. This time delay
(thirty-two pulses) corresponds to two bit periods, the UAR/T devices
having internal divide-by-sixteen counters so that a bit period is equal
to sixteen clock pulse outputs from the counter 63. When the gate 131
receives the input from the counter 134, the output of the gate 132
returns to high state, resetting the counters 134 and 135 and causing the
one-shot 133 to fire, producing a negative-going pulse output which is
applied to the two NOR gates 92 and 93. Since this signal is delayed by
two bits at the end of one byte, it will coincide with the first bit (the
"start" bit) at the beginning of the next byte unless there is no next
byte because the cycle has completed and the "dead" time is present at the
input to the unit 74A. It will be noted that each byte | | |
