A memory control system comprises a memory unit including a plurality of chips each having a shift register type memory having a plurality of information loops, the number of chips being larger than a predetermined number, the predetermined number of bits out of those bits which are read from or written into the information loops of the respective chips at the same timing constituting a unit information; and an additional memory which stores information indicative of normal loop condition or defective loop condition for each of the information loops in each of the chips and information indicative of whether the number of normal loops in each information loop group corresponding to the bits which are read or written at the same timing is larger than said predetermined number or not. Based on the information stored in said additional memory, only the predetermined number of normal loops are selected from the information loops corresponding to the bits which are read or written at the same timing, and when the number of normal loops does not reach the predetermined number, the information loops at that timing are not used.

A block replicate bubble memory device is provided with a plurality of series storage loops, wherein data words are written into or read out of the storage loops in parallel. The data is entered into write lines and is read on to read lines which are connected to the series storage loops approximately one-half of one loop time apart. Information in the storage loops is ordinarily changed or altered in no less than one-half of one loop time in the prior art. The present invention provides a plurality of bubble generators connected to the serial write line in a manner which permits several bubble device functions to be conducted in less than one-half of one loop time.

In a shift register type memory device wherein a plurality of chips are connected to a single sense amplifier and wherein data to be stored is cyclically written into the chips, then when a predetermined loop within a chip for stored designated data is defective, the data is not stored in a loop within the chip adjacent to the defective loop, but is stored in a loop to be subsequently read out in a chip to be read out subsequently to the chip having the defective loop.

A bubble memory system comprising data chips each having a plurality of storage loops and wherein each is provided with additional storage loops to compensate for defective loops in the chip, and a control chip having control loops, one loop for each data chip and with bit positions corresponding in number to the number of storage loops in the data chip and connected to the data chip to prevent defective loops on the data chips from being utilized. Thus, data chips which would otherwise have been discarded as defective can now be used.

A logic system is disclosed for using a memory device of the serial read type having redundant elements in excess of the nominal memory size and consists of a Programmable Read Only Memory having a defect map programmed into it with respect to the associated memory device, a shift register of a predetermined length equivalent to the maximum number of allowable defects, a multiplexer associated with the shift register, a position counter for controlling the multiplexer and, finally, appropriate logic to control the system. This system is disclosed in connection with a bubble memory system of the field access major loop -- minor loop type having extra minor loops. As defects are encountered in writing, data is shifted through the shift register while the multiplexer is incremented to the proper output position of the shift register based on the number of encountered defects. As data is read, an analogous reverse to writing operation is performed with the multiplexer being decremented. In either writing or reading, the multiplexer will never be shifted more than one position for each data bit.