A signal processor for use in a small, lightweight radar-guided missile to provide a discrete Fast Fourier Transform (FFT) on received radar return signals. The radar return signals are converted into a sequence of binary digits enabling a simple decoder to perform complex addition and subtraction processing, thereby minimizing the space and complexity of the signal processor.
An array (aperture) signal processor using surface acoustic wave delay lines for reordering of the received signals according to the prime number transform algorithm. The output of the processor is a radar response equivalent to forming a multiplicity of narrow beams essentially simultaneously. Reordering of the received signals is simply a matter of rearranging the hardwired connections to a first SAW delay line, and convolution of the reordered signals is achieved by phase weighting the taps in a second SAW delay line which forms part of a transversal filter.
Disclosed is a signal detector including a bank of digitally synthesized rowband filters all having the same shape of frequency response and differing only in center frequency and which are implemented by time domain data processing. The invention is comprised of: a signal conditioner, an envelope weighting computer, a Fourier transform processor and a post-detection processor. Resulting therefrom is a bank of 16 contiguous narrowband filters having high selectivity along with a corresponding bank of envelope detectors of wide dynamic range which incorporates center frequency acquisition and tracking. Following detection, a matched filter capability is included to provide correlation and data regeneration so that coded FSK data burst signals can be extracted in real time from noise, interference, and jamming signals which would otherwise affect signal detection.
A radar fuzing system for a guided missile is shown to include means for impressing a polyphase coded modulation on a transmitted signal and delayed replicas of such modulation on a bank of correlator/mixers, each one of the latter including dual gate field effect transistors as the active elements.
An FFT-like array architecture (500), for use on the Doppler filters of a radar system, includes a plurality of stages (505, 506) of weighted butterflies (501, 502, 503, 504), in which each butterfly is provided with four weighting multipliers (410-416). The weights (W1, W2, W3, W4) of the multipliers of the array are determined by an iterative process in which the input and output signals are selected, the input signals are applied to the array, and the actual output signals are compared with the desired output signals to produce error signals. The error signals are backpropagated through the array, to correct the weights. The input signals are again applied, and the corrected output signals are again compared with the desired output signals to produce new error signals, which are again backpropagated to correct the weights. This procedure is used iteratively until the array "learns" the weights which give the desired output signals. In a radar context, narrower Doppler filters and lower sidelobe result over a given range of frequencies.
An apparatus for performing a Fourier transform using Cordic techniques. Digital words are pipelined through serial add/subtract stages to provide vector rotations without trignometric lookup tables or multiply operations. The throughput of an FFT butterfly calculation is increased over prior art digital processors. A plurality of apparatus may be pipelined in a system to further increase the throughput rate. Also, the apparatus may be programmed to perform vector rotations through a plurality of angles thus providing the capability to compute FFT's of varying numbers of points.