A control store included in a data processing system for storing microinstructions in a plurality of microinstructions storage locations is organized in two parts, an upper bank and a lower bank. The lower bank is directly addressed by a portion of the currently addressed control store word, whereas the upper bank is addressed by use of a multiplexer, with inputs thereto coupled from various logic elements. Apparatus is included to determine which part of the control store will be selected and to allow such determination at a time substantially after the addresses for the first and second parts have been received by the control store. In addition, the elements included in the upper bank are selected to have address propagation time sufficiently faster than the address propagation time of the lower bank to compensate for the additional logic propagation delay introduced by the multiplexer so that the contents of the addressed locations of the upper and lower banks are available for use by the system at substantially the same time.

A technique to store a plurality of addresses and data to address and data buffers, respectively, in an ordered manner. More particularly, one embodiment of the invention stores a plurality of addresses to a plurality of address buffer entries and a plurality of data to a plurality of data buffer entries according to a true least-recently-used (LRU) allocation algorithm.

A cache clearing apparatus for a multiprocessor data processing system having a cache unit and a duplicate directory associated with each processor. The duplicate directory, which reflects the contents of the cache directory within its associated cache unit, and the cache directory are connected through a system controller unit. Commands affecting information segments within the main memory are transferred by the system controller unit to each of the duplicate directories to determine if the information segment affected is stored in the cache memory of its associated cache memory. If the information segment is stored therein the duplicate directory issues a clear command through the system controller to clear the information segment from the associated cache unit.

A cache/disk subsystem includes a host processor, a cache store, a disk drive device for driving a disk, and a storage control unit for controlling the transfer of data between the host, disk and cache store. The cache store holds segments of data which have been read from, or are to be written to, the disk. When the host issues a normal WRITE command to the storage control unit and none or a part only of the data from the disk space specified by the command is resident in the cache store, the segment or segments of data in the disk space are staged into the cache store and overlayed with data from the host. A directory in the host keeps track of the disk segments previously written to. When the host is ready to issue a WRITE command it checks the directory and, if the segment or segments to be written to have not previously been written to, then the host issues an ACQUIRE WRITE command. The storage control unit includes controls responsive to an ACQUIRE WRITE command for bypassing the staging operation. The storage control unit also includes circuits for converting a normal WRITE command to an ACQUIRE WRITE command when the beginning and ending addresses of a normal WRITE command fall on segment boundaries. The ACQUIRE WRITE command eliminates unnecessary staging from the disk to the cache store in situations where there is no data to be staged or all of the data which would be staged would be overwritten.

A tester of circuit devices is disclosed which uses commercially available component parts but is capable of high performance testing of hierarchical memory cards requiring data pulses of variable pulse widths at high repetition rates. The tester includes two memories connected to respective shift registers which in turn, feed a multiplexer. The memories handle test timing patterns for respective halves of the basic clock test cycle and are interleaved in operation along with the shift registers. Two opposite-phased outputs of the multiplexer are applied through respective programmable delay networks and pulse generators to the set and reset inputs of a trigger circuit. The trigger circuit provides test data to a dedicated input pin of the device under test.