A first in-first out buffer memory coupled to a system bus receives all information transferred over the bus. Logic associated with the buffer memory tests if the information received is intended to update main memory or is in response to a cache request. The information is written into cache if the main memory address location is stored in a cache directory. The information received in response to a cache request is stored in a cache data buffer. Other information is discarded.

The disclosed embodiments filter out many unnecessary interrogations of the cache directories of processors in a multiprocessor (MP) system, thereby reducing the required size of the buffer invalidation address stack (BIAS) with each associated processor, and increasing the efficiency of each processor by allowing it to access its cache during the machine cycles which in prior MP's had been required for invalidation interrogation. Invalidation interrogation of each remote processor cache directory may be done when each channel or processor generates a store request to a shared main storage. A filter memory is provided with each BIAS in the MP. The filter memory records the cache block address in each invalidation request transferred to its associated BIAS. The filter memory deletes an address when it is deleted from the cache directory and retains the most recent cache access requests. The filter memory may have one or more registers, or be an array. Invalidation interrogation addresses from each remote processor and from local and/or remote channels are received and compared against each valid address recorded in the filter memory. If they compare unequal, the received address is recorded in the filter memory as a valid address, and it is gated into BIAS to perform a cache interrogation. If equal, the inputted address is prevented from entering the filter memory or the BIAS, so that it cannot cause any cache interrogation. Deletion from the filter memory is done when the associated processor fetches a block of data into its cache. Deletion may be of all entries in the filter memory, or of only a valid entry having an address equal to the block fetch address in a fetch address register (FAR). Deletion may be done by resetting a valid bit with each entry.

A system and method for improving cache memory write cycle timing in a microprocessor system, having static random access memory (SRAM) cache memory, using two out-of-phase clock signals and delayed variants thereof. The present invention includes the steps of sending a write address to the cache memory at a positive transition of the first out-of-phase clock signal that marks the beginning of the write cycle; causing a write control signal to be asserted at a time marked by next occurring positive transition of the second out-of-phase clock signal; sending the data to be written to the SRAM at a time marked by a drive clock signal; and ending the write cycle at a time marked by a end-write clock. The drive clock signal is provided by delaying the first out-of-phase clock signal. The amount of delay introduced in providing the drive clock signal is selected to allow the SRAM sufficient time to tri-state its drivers after receiving the write-control signal. The end write signal is provided by delaying the second out-of-phase clock signal. The amount of delay introduced in providing the end-write clock is selected to allow the SRAM sufficient time to read data to be written off of the data bus. The delay is introduced into the clock signals using printed circuit trace delay lines. The length of the printed circuit trace delay lines is selected such that the drive clock and end-write clock transitions occur at the optimum time.

A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.

A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.