In a two-wire, full duplex data transmission system a circuit arrangement is described for carrying out an automatic adjustment of the value of the current flowing from the transmitter in a given station to a receiver therein relative to the value of the current supplied to that receiver from another station over a transmission line. A balancing circuit receives the station transmitter current and divides it into a plurality of sub-currents which are subsequently recombined and conducted to the station's receiver. The station transmitter current and the received current values are compared, and a voltage proportional to the difference is produced. That voltage is utilized by a regulating stage to produce a number of regulating voltages corresponding to the number of sub-current carrying branches in the balancing circuit for regulating the amplification of the sub-currents.
A duplex signaling circuit for signaling with respect to a line circuit includes a resistance bridge hybrid (22, 27, 28, 32) having a modified resistance makeup to reduce power consumption and improve longitudinal current immunity without altering conjugacy between signaling transmission (12) and receiving (17) connections to the bridge. An electronic relay emulator (86), which is responsive to bridge hybrid output signals representing received line circuit signals, provides relative immunity to noise and to pulse splitting for thereby relieving a hybrid balancing impedance capacitance (33) of those functions so that a compromise capacitor value can be selected for balancing a relatively wide range of signaling line circuits. A user-stepped, successive approximation, adjustment process for the balancing impedance is implemented in the signaling circuit.
The invention provides a current generating circuit with a single configuration, enhanced durability, and low power consumption. A circuit block C1 appropriately selects elemental currents i11 to i14 and i1F in accordance with data (bits) S11 to S14 and S14 and generates a sub-current Iout1. Similarly, a circuit block C2 appropriately selects elemental currents i21 to i24 and i2F in accordance with bits S21 to S24 and S2F and generates a sub-current Iout2. A circuit block C3 appropriately selects elemental currents i31 to i34 and i3F in accordance with bits S31 to S34 and S3F and generates a sub-current Iout3. A circuit block C4 appropriately selects elemental currents i41 to i44 in accordance with bits S41 to S44 and generates a sub-current Iout4. These sub-currents Iout1, Iout2, Iout3, and Iout4 are combined to generate a main current Iout.
