A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between the data bus and a peripheral device, such as a teleprinter. A first interrupt conductor is connected to the peripheral device and to interrupt logic circuitry in the interface adaptor. A second interrupt conductor is connected to the microprocessor and the interrupt logic circuitry. The interrupt logic circuitry is also coupled to and interrogatable by the microprocessor via the data bus. The interrupt logic circuitry stores interrupt contrl information from the data bus, and generates a second interrupt signal on the second interrupt conductor in response to the stored interrupt control information and an interrupt signal generated on the first interrupt conductor by the peripheral device. The interrupt logic circuitry also stores status information indicative of the occurrence of the first interrupt signal and effects interrogation of that status via the data bus.
Microprocessor apparatus for data exchange is controlled by information supplied via a microinstruction bus and a triggering line and transmits data from some external bidirectional data buses to other such buses. Data is supplied via data exchange units (1.sub.1, 1.sub.2, 2), internal bidirectional data buses and a switch. In addition to the transmission of information, the microprocessor apparatus can, depending on the code of the microinstruction, count the number of transmitted words via a counter and compare or mask data or arbitrate transmitted data via a data processing/converting unit. While executing microinstructions, the counter, the data processing unit, a register unit and a switch shape distinguishing features of the processed information, to be later fed to a conditional operation unit. The conditional operation unit shapes a generalized condition for readjustment of operation of a control unit.
A computer peripheral interface solves the problem of the interrupt-line mismatch between the PCI and ISA bus architectures without requiring additional interrupt lines between ISA devices and the computer. To accomplish this, a PCI-ISA bridge is provided that responds to ISA interrupts by generating a predetermined software interrupt instruction over the PCI bus. The peripheral interface includes a software-interrupt register and associated circuitry for accepting this software interrupt instruction and generating a corresponding simulated hardware interrupt. To solve problems associated with allowing two like-addressed devices to share a single bus, the computer peripheral interface uses a unique subtractive decoding scheme that allows the processor to selectively access either an internal floppy disk drive controller or a like-addressed peripheral floppy disk drive controller on the shared PCI bus.
In a system including a processor and at least one connector for providing inputs to the processor, which one of a plurality of different types of peripherals is plugged into the connector is determined by sensing any change in the connection of a peripheral to said connector, upon initial start-up of the system and each time a change from not plugged in to plugged in is detected interrogating the peripheral to obtain its type and storing the type of peripheral which is plugged in.
An information processor is comprised of a plurality of circuits each of which is controlled by firmware and connected to a common bus and has a contention circuit for the bus. An arithmetic control unit for controlling the execution of the firmware is provided with a timing control circuit. When the arithmetic control unit is going to issue a bus use request or has issued the request of when it is issuing an interrupt inhibit instruction or interrupts its operation, another unit connecting to the common bus seizes the bus and interrupts the arithmetic control unit. In such a case, the timing control circuit causes the execution timing of the arithmetic control unit to be in a wait state and accepts the interrupt.
Logic circuitry for use in electrical apparatus for providing an interrupt signal to a controller when there is a power failure in the electrical apparatus. The logic circuitry is connected to a bus from the controller. When the logic circuitry receives a power failure signal, it sets an interrupt state register and provides an interrupt signal on the bus as long as the interrupt state register is set. If the power failure signal no longer indicates a power failure, the logic circuitry responds to a signal from the controller indicating that the interrupt has been received by resetting the interrupt state register, thereby ending the interrupt. However, if the power failure signal is still active, the logic circuitry will not reset the interrupt state register in response to the signal from the controller. The logic circuitry is incorporated into a system having a plurality of individual electrical apparatuses, each of which is capable of generating an interrupt signal when it detects a power failure in itself, and a plurality of controllers, each controller having an associated bus connected to each individual apparatus such that the system can be configured to allow any selected one of said controllers to be connected to and control any selected one of said apparatuses. The logic circuitry receives the power failure signal from the selected apparatus, provides the interrupt signal to the appropriate controller and resets the interrupt state register under control of the controller if the power failure signal from the selected apparatus is no longer present.
