Units peripheral to a data processor and individually selectable by unique address signals to perform functions are arranged in sets providing functions of hard wired apparatus such as data modems, units in each set providing functions identical to corresponding units in other sets. The performance of the functions is controlled by a memory unit which designates which modem set is to be selected and by a common program routine which instructs the processor to apply, to an address bus, address codes defining corresponding units without specifying the individual unit. A logic circuit converts the address codes to the unique address signals of the corresponding unit in the designated modem set. At the end of the routine the processor changes the designation in the memory unit to another modem set. An interrupt routine instructs the processor to directly access individual units by applying, to the address bus, address codes defining individual units, which address codes are converted to the unique address signals of the defined individual units.
An input/output start instruction includes, as parameters, a channel number, an input/output device number, a channel control block address and a termination que number. A channel receives the channel control block address and reads out the contents of the channel control block from a main memory and sets it in a service table in the channel whereby an input/output processing is executed.
In a processor having a real address space larger than its virtual address space, all of the physical memory is addressed by using a separate prefix register associated with each of the address registers to hold both a high-order address portion and a control bit specifying whether the address is to be translated or used as a direct real address.
