A digital real-time signal processor is designed to be coupled to a computer. This processor includes a circuit of inputs/outputs, an input/output control circuit, a computer-coupling circuit, a buffer memory, digital signal-processing elements and a control circuit for the processing elements. The digital signal-processing elements are made up of a plurality of interconnected processing modules. Each module comprises an arithmetic unit, a high-speed multiplier, a shift register, a function memory, an addressable data memory containing all data handled by the processors of various functions, a sequentially operated address memory enabling scanning the data memory, and a microprogram memory. Each microprogram contains instructions capable of controlling the arithmetic unit, the multiplier, the shift register, and the waveform memory depending upon a particular configuration.

A radar seeker transient suppressor for an anti-radar homing missile in which glint effects upset the smooth tracking of a target by apparently changing the target position spasmodically. A seeker output signal is derived which is at least substantially independent of body movement e.g. the target sightline angle signal rather than the look angle signal (i.e. relative to a space reference rather than a body reference). This signal is used to control the steering either filtered or unfiltered according to whether the difference exceeds a threshold value or not. Both azimuth and elevation channels are treated similarly and in unison. An excessive filtered/unfiltered difference in either channel causes use of the filtered signal in both. A double integrating filter may be employed to avoid the relative displacement of output and input signals when the input is, or contains, a ramp component.

An operating circuit carrying out a conditional branch to judge a value level of a calculated result output from an arithmetic logic unit (ALU) during one machine cycle, using an address unit, realizes shorter processing time and low power consumption. The operating circuit sequentially carries out calculations according to command codes in a command ROM and includes a result register for storing and outputting the calculated result of the ALU; a value level judgement mechanism for judging a value level of an output of the result register; a latch for storing a current value of a program counter; an adder for calculating a next value of a program counter by adding a value level judgement result from the value level judgement mechanism and a current value of the program counter stored in the latch; and a first selector for selecting an added result and for deciding a next command address in the command ROM, a conditional branch being carried out to a command address corresponding to a value level obtained for the calculated result from the ALU.

In a protective relaying apparatus for an electric power transmission system and the like there is provided a nonvolatile memory device in which various values required for protection of the system are written electrically. An input device designates addresses in the memory device and memorizes values in the addresses under control of a control device. A digital processing device carries out the protective operations for the electric power transmission system based on the values thus set in the non-volatile memory device.

A data processor having an internal address bus and a separate internal data bus which are selectively coupled to an external memory bus. The external memory bus is time shared so that it can carry memory addresses as well as data. A command shift register, at least one capture register, a timer register, a compare register, a control register, and a status register are all coupled to the internal data bus. The command shift register is capable of serially shifting data, upon command, to an output terminal. The at least one capture register is capable of being loaded from the timer register whenever a transition occurs on a predetermined input to the data processor thereby capturing the time at which the transition occurred. The compare register is used to store a digital signal equivalent to some desired time. The compare register is continuously compared for equality with the timer register and provides a signal when equality exists. The control register is capable of providing software control of preselected registers within the data processor and the status register is used to temporarily store data indicating causes of interrupts.