In a data transmitting/receiving device having parallel/serial and serial/parallel character conversion, particularly for data exchange between communicating data processing systems, and being arranged between a local data processing system and a data modem terminating a data communication line for the purpose of controlling data transmission and/or reception procedures and containing a procedure store, and in which a random access storage is provided as a data buffer for intercepting data jams is provided along with an interrupt control for interrupting processing operations in a microprocessor in respect of higher processing priority, and in which a timer is provided for setting optimum transmission speed, first and second modem connection lines are provided and data messages to be transmitted are converted bit-oriented or character-oriented by the microprocessor from data groups supplied thereto by means of corresponding input switching commands. In addition, the optional transmission of bit-oriented data messages according to the synchronous data link control (SDLC) method or according to the high-level data link control (HDLC) method is provided.

For each of two computer systems, logic flowcharts describe background program in which highly detailed memory checksum tests of fixed memory and complementary tests of variable memory are performed, the background program being interrupted for utility programs which are for the most part responsive to transducer or other sensor and discrete inputs to calculate control values for operation of control actuators or other responsive devices. The utility programs include specific self test routines. A direct memory access unit is included in each computer for moving data between inputs of either computer and memories of both, and between the memories of both computers. Periodic testing of fault codes registering the health of each computer is done during utility program routines, any variation from normal causing further health-analysis routines to be performed until dispositive action-causing conditions are determined. Neither computer checks the internal health of other, but inputs, results and data link transmissions must compare equally between the two computers, or routines determine whether one computer will recognize itself (or a component thereof) as being faulty, and disable itself. If not, then each computer disables itself after disabling the other. A variety of self tests and other checks and routines are included. Disablement is accomplished in a complex fashion of each computer's output, by itself, and additional disablement if instituted by the other computer.

A data processing system includes a communications subsystem communicating with a number of devices. A counter monitors the communication line to detect when a communication line goes idle, that is at least 15 successive binary ONE bits appear on the line for the bit oriented protocol mode. The counter advances on successive binary ONE bits and is forced to a hexadecimal ZERO in response to a binary ZERO. If the counter reaches a count of hexadecimal F (decimal 15) a carry signal from the counter prevents the counter from advancing and initiates an idle link state.

The disclosed microprocessor support system provides a total "laboratory" environment for developing and testing application software as well as for debugging the microprocessor-based application machine itself. The microprocessor support system contains a time shared minicomputer equipped with a full set of peripherals which functions as the main or operating system. A data link connects this operating system with test equipment located at the site of the application machine. This test equipment consists of a field test unit which provides an interface between the application machine, a local keyboard terminal and the operating system such that an engineer at the site of the application machine has access through the field test unit to both the microprocessor-based application machine and the operating system with its sophisticated hardware and software resources to assist in developing and testing application software, as well as debugging the application machine itself.

The input/output system for a computer of this invention permits a peripheral device and its associated peripheral processor to be connected either (a) directly to the central processor unit of the computer, or (b) to a remote hardware peripheral control device which permits the central processor unit to directly control the peripheral processor, or (c) to a remote input/output controller which controls the peripheral processor independently of the central processor unit of the computer. The input/output system of this invention permits the use of the same software set stored in memory to control the input/output operations of a selected peripheral device regardless of where the peripheral device is connected.