A single chip large scale integration processor possesses its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function is also enhanced by providing a read only storage (ROS) array in association with the ALU to provide multiple register loading and control functions in response to certain addresses. The processor also includes memory control circuitry that permits a group of like processors to access a single, external memory on a dynamic, prioritized basis.
A method for dynamically altering Read-Only Memory (ROM)-based programs utilizes Random-Access Memory (RAM) and standard processor linkages associated with subroutine or function calls. Each original ROM program includes a statement to call a ROM processing routine. If information passed to the processing routine by the original routine indicates a RAM-based replacement routine is to be executed for the original routine, the processing routine (i) restores the processor to its state immediately following the call to the processing routine, and (ii) branches directly to the replacement routine at a location provided by a RAM-based data structure.
To facilitate the expansion and addition of instruction functions and to reduce development costs and time for products comprising new functions, the microaddress and mask address of a microinstruction are compared by a microaddress comparing circuit. When they correspond, an extended micropointer for generating an extended microaddress is selected by a pointer selecting circuit so as to access extended microinstruction memory in place of the micropointer and to exchange the function of a microinstruction specified by a microaddress with the function of an extended microinstruction.
A digital processing system includes an external memory for the storage of program instructions for use with a separate processor that internally contains a memory for temporary storage, an arithmetic and logic means, a register set, control and timing circuitry, and two sets of data paths. The first set of data paths provide access to the external memory for transfer of instructions from the external memory to the processing unit. The second set of data paths provide for the internal routing of instructions data and addresses within the processor unit itself. The data structure for the first set of data paths is different than that for the second set of data paths, providing for an external data structure that is different than the internal data structure of the processor.
A microprocessor external instruction feature which provides for a single chip microprocessor with on-chip read only instruction store (ROS) that can also be operated with an off-chip instruction store. To accomplish this, the microprocessor instruction sequencing logic (instruction store, instruction register, instruction counter, and sequencing logic) is duplicated off-chip. An XI MODE input pin signal causes the microprocessor to take its instructions from the external instruction store via 12 XI input pins instead of from the on-chip ROS. A BR DECISION output pin signal from the microprocessor, which indicates that the branch conditions have been met, causes the external instruction counter to be loaded with a branch address from the external instruction register instead of being stepped by external sequencing logic. A WAIT output pin signal causes the external instruction feature logic to suspend operations while the microprocessor is in its wait state.
A single-chip microprocessor device of the MOS/LSI type contains an ALU, internal busses, address/data registers, an instruction register, and control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by control lines and a bidirectional multiplexed address/data bus. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM not in the main off-chip memory map) is provided which allows execution of instruction sequences to emulate complex instructions or interpretors (macro-instructions). The macro-instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. Also, off-chip access of another memory separate from the main memory allows emulator functions or special instructions.
