 |
Description  |
|
|
This invention relates to light controllers and more particularly to theatre
and television light dimming systems and the like.
Theatre light dimming systems are used to control a plurality of lights usually of different colors. The lights are connected to power dimmers so that the intensity of each of the lights can be controlled collectively, individually or in groups
so as to provide a variety of different combinations of lighting levels for achieving a variety of different lighting effects (called lighting "cues"). Typically, each light or group of lights is selectively controlled through a power dimmer, which in
turn is connected to an individual controller or operator switch. In such a system separate sets of wires typically run from the controllers, typically located on a control console board in a light operator'3 booth, in the rear of the auditorium through
the power dimmer to each light or group of lights located on the stage. Thus, even for small and medium sized installations, usually found in high school and college auditoriums and community theatres, where there are about 50 power dimmers, a large
amount of wiring is necessary to connect all of the lights with their respective power dimmers and in turn the power dimmers to the controllers.
Many commercially-available theatre light dimming systems employ a memory unit, in the form of banks or arrays of potentiometers, for storing cues. Typically, the control console includes switches for selecting a particular array of
potentiometers. Accordingly, a light operator can present a cue, i.e., preset the light intensity of the lights controlled by each of the controllers by setting the potentiometers of one array of the memory unit. At the appropriate time, the operator
can then switch the array of preset potentiometers into the circuit through the control console so that all of the lights on the stage are set at their appropriate level. By way of example, the system presently employed in the Loeb Drama Center in
Cambridge, Mass., is provided with 52 controllers and power dimmers and employs 10 arrays of potentiometers as a memory unit. Thus, 520 potentiometers are employed which store up to 10 cues at any one time. The settings of each of the potentiometers
for each cue are typically determined at rehearsal, with a lively production requiring as many as 200 lighting changes, some of the changes involving up to 150 lights. Due to the limited memory capacity of the arrays of potentiometers, it is therefore
necessary that the operator set many of the cues during such a performance. Since he must set each of the potentiometers in each array separately, it can be demanding on the operator, particularly where several cues must be set in a relatively short
period of time. Further, these 520 potentiometers (1) take up most of one wall in the operator's booth, and (2) create a great deal of heat as well as power loss. Additionally, these potentiometers are notorious for attracting dirt and breaking down
under use.
It is a general object of the present invention to provide a light controller system which overcomes many disadvantages of the prior art system described.
More specifically, it is an object of the present invention to provide a light controller system in which the amount of wiring used to connect the control console to the individual power dimmers is substantially reduced.
Another object of the present invention is to provide a light controller system having a single bus to which any number of individually-controllable lights can be attached without appreciably increasing the amount of wiring.
Another object of the present invention is to provide an improved light dimming system in which an unlimited number of cues can be stored prior to the performance, and yet modifications to the cues can easily be effected during the performance.
Yet another object of the present invention is to provide a theatre light dimming system which can perform some of the same functions as the prior art system previously described, such as proportional mastering, dimmer control output and storage
of lighting cues.
Still another object of the present invention is to provide an improved theatre light dimming system, operable from a light operator's booth, requiring a relatively small amount of space, generating little or no heat, and providing a greater
immunity to a dirty environment.
A further object of the present invention is to provide an improved light control system with substantially less power consumption.
Another object of the present invention is to provide a light controller system having a single input control device bus to which any number of dimmer controllers can be attached without appreciably increasing the amount of wiring.
These and other objects are achieved by a light control system comprising improved control means for generating a first signal representative of a predetermined current level to be applied to a particular light group defined to include one or
more lights. Signal generating means is provided for generating a unique and predetermined serial binary-coded address signal corresponding to the particular light group and a serial binary-coded data signal, responsive to the first signal and
representative of the current level to be applied to the light group. Improved receiver means provides the predetermined current level to the particular light group only in response to the unique address signal. A common bus is utilized for
transmitting the address signal and the data signal from the signal generating means to the receiver means. Information storage and retrieval means are employed for storing any desired number of cues.
Other objects of the invention will in part be obvious and in part appear hereinafter. The invention accordingly comprises the apparatus possessing the construction, combination of elements, and arrangements of parts which are exemplified in the
following detailed disclosure, and the scope of the application of which will be indicated in the claims.
For a fuller understanding of the nature and objects of the present invention, reference should be had to the following detailed description
taken in connection with the accompanying drawings wherein:
FIG. 1 is a block diagram of a prior art theatre dimming system;
FIG. 2 is a block diagram of the preferred embodiment of the present invention;
FIG. 3 is a front view of the control console of the FIG. 2 embodiment;
FIG. 4 is a cross-sectional view taken along line 4--4 of FIG. 3;
FIG. 5 is a partial plan view taken along lines 5--5 of FIG. 4;
FIG. 6 is a circuit schematic diagram of the optical fader and dimmer control switches;
FIG. 7 is a circuit schematic diagram of the manual-off preset switches;
FIG. 8 is a circuit schematic diagram of the store and load controls;
FIG. 9 is a circuit schematic diagram of the preset selector;
FIG. 10 is a circuit schematic diagram of the receiver of the present invention; and
FIG. 11 is a timing diagram on a common time base useful in describing the operation of the receiver of FIG. 10.
In the drawings, the same numerals are used to denote like parts.
Referring to FIG. 1 of the drawings, a typical prior art system is shown as including the memory 16 which is connected through conductors 18, control 10 and wires 14 to the
power dimmers 12. The memory 16 includes a plurality of arrays of potentiometers (not shown) for storing cues, with a small to medium-sized system typically employing about 50 channels, one for each controller. Each array of the memory 16 includes an
equal number of potentiometers. Control 10 allows the operator to select which array is connected into the system for delivering a predetermined amount of current to each power dimmer 12. The output of each of the power dimmers is connected through the
patching network 20 and wires 22, to the individual loads 24.
This system has its disadvantages including (1) the memory 16 is limited in cue storage capacity; (2) the potentiometers of the memory attract dirt which can cause malfunctioning; (3) the potentiometers generate a large amount of heat providing a
relatively large power consumption loss and (4) the setting of the potentiometers can involve a great effort on the part of the operators. Further, the amount of wiring required is rather large, since the required number of wires 14 are equal to the
number of channels plus one for ground, and expensive since each of the wires 22 are typically of a large gauge so that they can carry up to 50 amps and are wired from the centrally-located network 20 to the various loads 24 at various locations in the
theatre.
In accordance with the present invention, these, as well as other disadvantages which may be apparent to those skilled in the art, are substantially overcome by the light control system shown in FIG. 2. The system of FIG. 2 performs all of the
functions of the traditional system of FIG. 1, e.g. proportional mastering, dimmer control output and storage of sets of lighting levels (cues). The system includes a memory and control system 32 which is preferably contained in a single console unit,
generally designated 30, so as to minimize space requirements and reduce heat and power losses encountered in the prior art system of FIG. 1.
The memory and control system 32 of unit 30 is preferably in the form of an information storage and retrieval system making possible the ability to store an indefinite number of cues and perform all of the necessary control functions. System 32
may be any one of several types of systems known in the art. For example, a microprocessor such as the one provided in the Design Evaluation Kit M6800 manufactured by Motorola, or a dedicated computer such as a PDP-11 manufactured by the Digital
Equipment Company of Massachusetts can be used. For a discussion of the M6800 microprocessor and the PDP-11, see for example, Sovcek, Branko, Microprocessors and Microcomputers, John Wiley and Sons, 1976, pp. 299-340 and pp. 469-513, respectively.
The type of system used is largely dependent upon the capacity desired. Therefore, for purposes of illustration and for ease of understanding, the present invention and in particular system 32, will be described with respect to the Motorola Design
Evaluation Kit, M6800. This system includes a microprocessor which can be programmed to carry out the functions enumerated hereinafter. The microprocessor is designed so that a variety of logical and arithmetic operations may be performed on or between
the two accumulator registers including additions, subtractions, logical AND'3, OR's, compares, compliments, tests and shifts. Four dedicated registers (not shown) are used in the control of the system: a program counter, an index register, a stack
pointer, and a condition code register. These are generally controlled by the microprocessor logic, although they may be used or altered under program control.
System 32 also includes a ROM (read only memory) commonly referred to as MIKBUG by Motorola. This ROM contains a program provided by the manufacturer which allows a programmer to communicate with the processing unit 32. The program allows user
programs and data to be stored in memory, the working registers to be examined, and the execution of the user program to be supervised. System 32 also includes RAMs (random access memories). The number of RAMs required is dependent upon the storage
capacity desired. Two RAMs are provided in the Motorola kit as well as means for attaching additional RAMs. Two segments of the RAMs, designated separately in the drawing as registers 33A and 33B are used to store two active cues, the purpose of which
will be made more apparent hereinafter.
The microprocessor system 32 communicates with the other elements of the light control system over three buses 34, 36 and 38. The components of the system 32 are connected to the address bus 34 through one-half of a Peripheral Interface Adaptor
(PIA), designated A, while the system is connected to the data bus 36 through the other half, PIA B. The PIA, being part of the Motorola kit, serves the function of allowing the input and output of data to and from the components of the microprocessor
system. The microprocessor is programmed to essentially instruct the PIA A which channel to look for by providing a binary-coded output to the address decoder 40. Decoder 40 preferably is a binary one-out-of-10 decimal converter which produces enable
signals to the particular external peripheral devices 42 (which include the various switches and preset selector as described hereinafter) addressed. The system 32 is thus ready to receive data over data bus 36. The data is received over bus 36 through
the PIA B. The address bus is thus designed so that the peripheral devices respond to particular addresses. The data bus 36 handles transfers between the peripheral devices and the microprocessor. Each PIA is adapted to handle two channels of 8-bit
parallel data. In each channel, a buffer register is connected to the data bus. One memory address connects the buffer to a condition code register, which can be read or changed by the microprocessor. This sets the data direction format, and
determines whether or not the PIA can interrupt the data processor. The next sequential address activates the data register, the latter doing the actual communicating. The Motorola microprocessor also uses a PIA to handle communication with a teletype
machine indicated generally as TTY. The latter provides an input and output to the memory so as to change the program if desired. Finally, the system 32 is connected to signal bus 38 through the Asynchronous Communications Interface Adaptor (ACIA), the
latter being included in the Motorola kit. Like the PIA, the ACIA has a control and a data register wired to different addresses. The ACIA of the kit requires an external signal clock 41. By way of example, a crystal-controlled baud rate generator is
a suitable clock although other clocks can be used. In addition to providing a clocking signal to the ACIA, the clock 41 also provides a clocking signal over one of the wires of the bus 38 and is used to transfer the signals over another wire of the bus
38. In the output mode, the ACIA receives a data word from the microprocessor and transfers it into the data register. The condition codes determine the trnsmitting rate, and the number of start, stop and parity bits required (as will become more
apparent hereinafter in connection with FIG. 11). The complete word is shifted out of the register over bus 38 at the given clock rate. Once transmission is begun over bus 38, one of the condition code bits is changed to indicate that the ACIA is able
to accept another data word. The program of the microprocessor always checks this bit before attempting to load the ACIA. In this way, the ACIA is used to transmit word sets, each of which comprises an ADDRESS word and a DATA word (both words being in
the form of serial binary-coded signals) to the individual receivers 44. Each receiver 44, described in greater detail with reference to FIGS. 10 and 11, is adapted to examine each word set and applies a current level represented by the DATA word to the
particular power dimmer 12 only when the DATA word is accompanied with the unique ADDRESS word to which the particular receiver is responsive. Thus, different current levels can be selectively applied to the individual loads 24 over the common bus 38 by
addressing the particular current level to the desired receiver or receivers.
Referring to FIGS 3-5, the control and memory unit 30 is described in greater detail. The unit comprises various peripheral devices including master faders (MFa and MFb) 50A and 50B, a manual master fader 52 and individual dimmer controllers or
switching means 54, one for each power dimmer 12. Only three controllers 54 are shown for ease of exposition but it will be appreciated that any number of controllers can be employed depending on the number of individual power dimmers that are to be
selectively controlled. Thus, each controller 54 is used to control the setting of the light intensity level of a light group, whether the setting of that particular light group is to be stored in the unit 32 or used to directly control the light group
on the stage. As will become more evident, hereinafter the manual master fader 52 is used to manually control the light intensities of the light groups on stage while the master fader 50A and 50B are used to control the light intensities of the light
groups on the stage through the registers 33A and 33B reqpectively of the unit 32. The faders 50 and 52 are controllers 54 are constructed substantially identically as shown in FIGS. 4 and 5 (with the exception that fader 50A is mounted oppositely to
fader 50B). Each fader 50 and 52 and controller 54 includes a handle 56 extending from the exterior the unit 30, where it can easily be grasped by the operator, through a slot 58 provided in the face plate 60 of the unit where it is attached to an array
of photosensitive elements 62 within the unit (see FIG. 4). The elements 62 are adapted to convert light energy into electrical energy. The array of photosensitive elements 62 preferably comprise seven phototransistors mounted adjacent one another in a
linear array, although it will be obvious that more or fewer elements can be used as well as other types of sensing devieces. The handle 56 and elements 62 are suitably mounted in the unit so that the handle can be manually moved in the slot 58 parallel
to the face plate 60 with the level of intensity of the lights being controlled gradually changing from zero to some full predetermined level as the handle is moved from a first (hereinafter indicated as 0) to a second (hereinafter indicated as 1 )
position.
A photomask 64 is mounted within the unit 30 by suitable supports 66 so that the photomask is positioned adjacent the elements 62, parallel to the movement of the latter. The photomask is preferably a glass or plastic sheet having a layer of
opaque material disposed on one side. The layer of opaque material is provided with light transmitting slits or tracks 68 (see FIG. 5). Although not shown in explicit detail, the tracks 68 are preferably arranged in what is commonly known as a Gray
code pattern. Gray codes are generally well known in the art. For example, see Fink, Donald G., Electronics Engineers Handbook, McGraw-Hill Book Company (1975) pp. 22-23, 24 and 29. Sepcifically, the tracks provide analog-to-digital conversion of the
position of the array of elements 62 with respect to the tracks 68. The tracks are disposed parallel to one another and to the direction of movement of the photosensitive elements 62. Each track is disposed adjacent to a corresponding one of the
elements 62 along a preselected portion or portions of the path of the element. The tracks transmit light from the light source 70 positioned below the photomask 64 to the elements 62 so as to divide the positions of the array of photosensitive elements
62 into a plurality of discrete positions, the number of which equals 2.sup.n where n equals the number of elements 62. Thus, by way of example, where seven elements are used, as the handle 58 is moved from the 0 position to the 1 position, the array of
photosensitive elements moves through 128 discreet positions. In the 0 position, none of the tracks transmit light to the photosensitive elements 62 so that the light group being controlled is set at zero intensity. As the handle 56 and the
photosensitive elements 62 are moved to the end, the first incremental change is such that only the track 68A is transmissive transmitting light to the photosensitive element 62A so that the latter provides an electrical signal. This represents the
number 1 in Gray form. In this position none of the other photosensitive elements 62B-G will receive light and thus will not generate electrical signals. At the next incremental position only the tracks 62A and 68B will be transmissive thereby
energizing photosensitive elements 62A and 62B so that the latter generate electrical signals. This represents the number 2 in Gray form. In this position none of the other photosensitive elements 62C-G will receive light and thus will not generate
electrical signals. At the next incremental position only track 68B will be transmissive so that photosensitive element 62B generates an electrical signal while elements 62A and 62C-G do not. This represents the number 3 in Gray form. Accordingly, the
elements 62A-G represent bits of information corresponding to a Gray code indication of the positions of the elements 62. Although other patterns can be used with greater or fewer increments (by increasing or decreasing the number of elements 62 used)
it was found that a pattern approximately 10 centimeters long having 127 increments was adequate to insure that enough light was transmitted through the particular tracks to energize the corresponding photosensitive elements providing very clean
switching with no problems arising from oscillation.
Each controller includes means for converting these Gray-coded signals to a parallel binary-coded set of signals and means selectively enabled by system 32 so as to instruct the system 32 as to the position setting of the controller. The means
can be in the form of software, in system 32, so that the Gray-coded signals are transmitted directly to system 32 and converted to binary form. The preferred means for converting the Gray-coded signals to parallel binary-coded set of signals is,
however, in the form of hardware and shown in FIG. 6. In the case of the controllers 54, means are also provided for selectively directing the setting of the particular controller to either directly control the light group controlled by the particular
controllers 54 or storing the setting in system 32. The output of each of the elements 62 is preferably shaped by applying the signals from the elements to suitable signal conditioning means such as Schmidt triggers. Schmidt triggers are well known in
the art and may take various forms. As shown, the triggers are each in the form of a NAND gate 74. The gates 74A-74G, each provide a sharp on-off transmission to provide a more sharply defined signal when the respective photosensitive element is
energized. An eitht NAND gate 74H is provided which shapes an ENABLE signal (the purpose of which will be described hereinafter) received from the PIA A of the system 32. The output of each NAND gate 74 is transmitted through a gray-to-binary decoder
76. Such decoders are well known in the art. In the preferred embodiment decoder 76 includes eight exclusive OR (EXOR) gates 78A-H.
The outputs of each of the gates 74A-F and H are applied to an input of the respective EXOR gates 78A-F and H of the converter 76 while the input of EXOR gate 78F is adapted to receive the output of gate 74G. The output of EXOR gate 78B is
connected to the other input of EXOR gate 78A and the output of EXOR gate 78C is connected to the other input of EXOR gate 78B. Similarly, the other input of EXOR gate 78B is connected to the output of EXOR gate 78C, the output of EXOR gate 78E is
connected to the input of EXOR gate 78D, the output of EXOR gate 78F is connected to the input of gate 78E. One input of EXOR gate 78G is connected to a positive voltage while the other input of gate 78G in the case of the master fader switches 50 and
master manual fader 52 is connected to ground (not shown). In the case of each of the controllers, the other input of gate 78G is connected to pole 1 of the corresponding MOP switch 82 (to be described hereinafter in reference to FIG. 7). The output of
EXOR gate 78G is connected to an input of NAND gate 74H. The output of NAND gate 74H is connected to the input of EXOR gate 78H. The output of the latter provides the enable signal E.
As will be more evident hereinafter, the output signal E of gate 78H, is at a logic high if the PIA enable line is high and in the case of controllers 54, the MOP switch is not in the off position. A manual-off-preset (MOP) switch 82 (shown in
FIG. 3 and in greater detail in FIG. 7) is provided for each controller 54 and preferably is a double pole, double throw center-off switch which has three positions: manual, off and preset. (1) When the MOP switch 82 is placed in the manual position the
corresponding controller 54 directly controls the power dimmer, (2) when switch 82 is placed in the preset position the power dimmers are controlled by the values stored in the memory of system 32 in conjunction with master faders 50 and (3) when the MOP
switch is placed in the off position the controller will have no effect on either the values in the working registers or the lights on the stage. As shown in FIG. 7 (1) when MOP switch 82 is in the manual position pole 1 is low and pole 2 is high, (2)
when in the preset position, both poles are low and (3) when in the off position pole 1 is high. Returning to FIG. 6, the outputs of the gates 78 of the gray-to-binary code converter 76 are connected to a set of control, open-collector NAND gates
indicated as 80A-H. All of the gates 80A-80H have an input connected to receive the enable signal E from the output of NAND gate 78H. Thus, the gates can only be enabled when the PIAA enable is high and the MOP swtich is either in the manual or preset
position so that the MOP pole 1 line is low. Gates 80A-80F each have their other input connected to receive the outputs of EXOR gates 78A-78F, respectively. The other input of gate 80G is connected to the ouput of the NAND gate 74G while the other
input of NAND gate 80H is connected to receive the signal from the MOP switch pole line 2. The outputs of the gates 80 thus provide an 8-bit parallel binary signal which appears on bus 36. Each of the first seven lines indicated as 0-6 are high or low
depending on whether sensors 62A to 62G are energized. The eighth bus line indicated as 7 will be low if the MOP switch is set on manual while it will be high if the MOP switch is set on preset. In this way the line 7 of the bus tells the
microprocessor of system 32 what to do with the data on bus lines 0-6, i.e. either to direct it to the working register for subsequent storage or to the lights on the stage. It is noted that if the MOP switch is off, the MOP pole line 1 will be high and
therefore the output of NAND gate 74H will remain low regardless of whether the PIA enable line is high or low.
It will be appreciated that since the master faders 50A and 50B and the master manual fader 52 are not provided with MOP switches, the circuitry of these faders 50 and 52 are identical to that of the controllers 54 shown in FIG. 6 except that the
MOP pole line 1 is connected to ground to provide a low signal input to EXOR gate 78G and the NAND gate 80H is not used. Thus, only a seven line output is provided (indicated by lines 0-6) to the system 32. When setting a particular light intensity
with any of the faders 50 or 52 or controllers 54, the handle 56 of the particular controller is moved between the 0 and 1 positions depending on the light intensity level desired. By moving the handle 56 of the particular controller, various
combinations of the photosensitive elements 62 are energized. When the desired intensity is achieved, the array of elements 62 are left in a fixed position relative to the photomask 64.
By way of example, as shown in FIG. 6, if only phototransistor 62A is energized, the output of NAND gate 74A will go high while the outputs of NAND gate 74B-G will remain low. This results in the output of EXOR gate 78A of the Gray-to-binary
decoder 76 and thus the input to NAND gate 80A to go high while the remaining outputs of the encoder remain low. In the case of controller 54, where the MOP switch is set on manual, pole line 1 will be low and pole line 2 will be high, while in the case
of the faders 50 and 52, line 1 is low and line 2 is not used. In either case, the output of the EXOR gate 78G thus is high enabling gate 74H when the PIA A enable signal is received from the system 32. When the gate 74H is enabled, the output of the
gate goes low enabling gate 78H of the decoder 76 providing the enabling signal to the NAND gates 80. Since gates 80A (in both cases) and 80H (in the case of controllers 54) are the only two gates enabled in the example given the output lines 0 (in both
cases) and 7 (in the case of controllers 54) of the bus will go low while the remaining lines will remain high. Since the output of gate 80H (in the case of the controllers 54) and thus line 7 of the bus goes low, the system 32 is instructed that the
MOP switch is set on manual and the signals provided on the bus from the controller are to be applied directly to the light group.
In the case of the controllers 54 where the MOP switch is set on preset, the MOP pole line 1 will remain low, as previously described, so that when the PIA A enable signal is provided, the output of the EXOR gate 78H will go high to enable those
NAND gates 80 having their other input in a high state. However, when the MOP switch is in the preset condition, pole line 2 will be in a low state so that NAND gate 80H will not be enabled and, thus line 7 of the bus will remain high.
Finally, in the case of the controllers 54, when the MOP switch is in the off position, the pole one line will be in a high state. This disables the exclusive OR gate 78G so that the output of NAND gate 74H remains high regardless of the PIA A
enable signals received at its input. Thus, the output of the exclusive OR gate 78H will remain low and the NAND gates 80 will not be enabled.
Referring again to FIG. 3 and more particularly to FIG. 8, in order to store particular cues in the microprocessor of system 32, a store switching circuit comprising four store switches is provided. All the switches are shown as the push-button
type, however, it will be obvious to those skilled in the art that other types of switches are equally satisfactory. As will be more evident hereinafter: (1) the manual store switch 100 is pushed when it is desired to store those values provided by the
setting of each of the controllers 54; (2) the stage store switch 102 is pushed when it is desired to store those lighting values currently on the stage; (3) the MFa store switch 104 is pushed when it is desired to store the values of the intensity
levels of those light groups in the storage register 33A of unit 30 multiplied by the proportional setting (0-1) of the MFa fader 50A; and (4) the MFb store switch 106 is pushed when it is desired to store the values of the intensity levels of those
light groups in the storage register 33B of the unit 30 multiplied by the proportional setting (0 to 1) of the MFb switch 50B. One terminal indicated as A of each of the switches is connected to a positive voltage source while the other contact
indicated as B or each of the switches is connected to the D input of the corresponding D-type flip-flops 108, 110, 112 and 114, respectively. The B terminals of the switches 100 and 102 are connected to the NOR gate 116 while the B terminals of
switches 104 and 106 are connected to the inputs of NOR gate 118. The outputs of NOR gates 116 and 118 are connected to the input of NAND gate 120. The output of the latter is connected to the input of NAND gate 122. the outputs of NAND gates 120 and
122 are biased through resistors 124 and 126, respectively, by a positive voltage source. The output of NAND gate 122 is also connected to the input of one-shot 128. One-shots are well known in the art and generally are a class of multivibrators.
One-shot 128 is designed so that when the output of NOR gate 122 provides a negative going transition (a change from a high logic state to a low logic state) after a predetermined period of time, the one-shot provides a positive going transition (a
change from a low logic state to a high logic state). This positive going transition output of one-shot 128 is provided to the E inputs of the flip-flops 108, 110, 112 and 114. The Q outputs of flip-flops 108, 110, 112 and 114 are connected to an input
of the respective NAND gates 130, 132, 134 and 136. The output of NAND gate 122 is also connected to the clocking input of the J-K flip-flop 138. The K input of flip-flop 138 is connected to a positive voltage source while the J input is connected to
ground. The Q output of J-K flip-flop 138 provides an interrupt request signal to system 32 when a negative-going transition is provided at the clocking input of flip-flop 138. System 32 provides an enable signal to the clearing input of J-K flip-flop
138 as well as to the input of each of the NAND gates 130, 132, 134 and 136. The output of NAND gates 130, 132, 134 and 136 provide a 4-bit parallel signal output over bus line 36.
In the steady state condition when none of the switches 100, 102, 104 and 106 are pushed, it will be appreciated that the inputs to NOR gates 116 and 118 are all low and the output of the two gates are high. The output of gate 120 accordingly is
low and the output of NAND gate 122 is high. Since the output of one-shot 128 is only high when the output of NAND gate 122 provides a negative going transition, the output of one-shot 128 will be low so long as the output of NAND gate 122 remains high. Similarly, the same negative-going transition from NAND gate 122 provides a high clocking input to the J-K flip-flop 138. In this condition, the Q output of the J-K flip-flop 138 will go high providing an indication to the system 32 that one of the
switches has been pushed. When so indicated, system 32 provides a high signal over the enable line so as to clear the J-K flip-flop 138 and to enable the appropriate NAND gate 130, 132, 134 or 136.
Specifically, by way of example, if it is desirable to store those values of the light levels provided by the setting of the controllers 54, switch 100 is pushed providing momentary contact between terminals A and B of the switch so that a high
pulse signal is generated. This high pulse signal is applied to the D input of the D flip-flop 108 and is also applied to the input of NOR gate 116. The output of NOR gate 116 accordingly changes from a high to a low signal. This provides a low signal
to the input of NAND gate 120 so that the output of NAND gate 120 goes from low to high. NAND gate 122 acts as an inverter and inverts the high output of NAND gate 120 to provide a negative going transition at its output. This transition triggers the
one-shot 128, which after a short delay produces a low to high transition at its output. The output of one-shot 128 thus enables the D flip-flop 108 whose high input now appears at its Q output and at an input to NAND gate 130. The negative-going
transition output of the NAND gate 122 is also provided to the clocking input of the J-K flip-flop 138, which in turn provides the (high) interrupt signal to system 32. System 32 thereby provides the enable signal (1) to the clearing input of the J-K
flip-flop 138 so that the Q output of the latter changes from a high to a low state and (2) to the NAND gate 130 (both of the inputs now being high) so that the output of NAND gate 130 changes from a high to a low state. The output of gate 130 remains
low for the duration of the enable signal from system 32 and then returns high. In this way, a negative going pulse is provided over the zero line of the data bus 36 indicating that switch 100 has been pushed. The system then provides the PIA enable
signal to each of the controllers 54 as shown in FIG. 6. In a similar manner, pushing switches 102, 104 and 106 provide a similar low pulse over the lines 1, 2 and 3 of the bus line 36 respectively so that the appropriate signal levels of the lighting
groups can be stored.
In order to load particular cues from storage into registers 33A and 33B of the microprocessor, two load switches are provided. These load switches operate in the same manner as the store switches except that since only two switches are
necessary, the FIG. 8 circuit can be modified by eliminating switches 104, 106, the flip-flops 112 and 114, NOR gate 118 and NAND gates 120, 122, 134 and 136. As shown, switch 100 is used as load switch A, hereinafter referred to as switch 100A, and
switch 102 is used as load switch B, hereinafter referred to as switch 100B. Accordingly, a two line output is provided over bus line 36 to indicate whether a particular setting is to loaded into register 33A or register 33B.
In order to instruct the microprocessor unit 32, the controlled unit is provided with a preset switching selector 150 (see FIG. 3) in which the unit can be instructed as to which cue is either to be used for storage or to be loaded into the
registers. For example, a thumb wheel switch providing an octal type output may be utilized to provide eight outputs indicative of eight corresponding positions of the thumb wheel switch. Such a switch is connected to the circuit shown in FIG. 9. Each
of the output lines indicated at 152, 154, 156 and 158 are connected to an input of the respective NAND gates 162, 164, 166 and 168. The other inputs of the NAND gates 162, 164, 166 and 168 are adapted to receive an enable signal from microprocessor
unit 32. Accordingly, when the enable signal is received providing a high input on the enable inputs of NAND gates 162, 164, 166 and 168 the output of the NAND gates will go low if the corresponding input of lines 152, 154, 156 and 158 is also high.
Thus, the output of NAND gates 162, 164, 166 and 168 is a parallel binary coded signal indicating | | |
