A digital communication system for the transmission of digital data with a modulated carrier uses a modulation locked loop and pseudo-random code to develop synchronization signals for the digital data signals and to ensure a high level of communication reliability.
BACKGROUND OF THE INVENTION
This invention relates to a system for radio navigation and communication and which may be employed for either or both.
This application is a division of application Ser. No. 389,796, filed Aug. 20, 1973, now U.S. Pat. No. 4,004,237; which was a continuation-in-part of application Ser. No. 33,748, filed May 1, 1970, and issued on Aug. 28, 1973, as U.S. Pat. No. 3,755,816; the latter application describes a system for radio navigation measurements that uses a modulation code signal which may take various forms, such as a rectangular wave modulation. The disclosure of that application is incorporated herein by reference. Where more complex navigation codes such as pseudo-random code are employed (e.g., for greater accuracy and to avoid ambiguities in global navigation), it has been found desirable to employ a modified form of modulation locked loop.
A unipolar, RZ, constant width pulse telemetry is achieved in the combinatorial set, or any desired subset of pulse sequences thereof. Each input datum W is in one-to-one correspondence with a particular pulse sequence and the correspondence of datum with pulse sequence and vice versa is implemented by any selected ordering of the pulse sequences of the combinatorial set together with a successive comparison of the magnitude of the datum with the cumulative combinatorial capacity of the set.
The present invention has an object to provide a matched filter circuit which is possible to synchronize a spreading code with an input signal. A matched filter according to the present invention samples input signal in response to three clocks from the first to the third shifted by a half cycle of a sampling signal so as to judge whether the sampling clock is ahead or behind of the input signal according to signs of input signal sampled. One clock is selected to be the sampling clock.
The invention relates to a method and apparatus for synchronization of transmitters and receivers in digital transmission systems of the OFDM type. The system uses FFT technique to carry out the modulation and demodulation procedures. According to the invention, the transmitter sends synchronization frames with known frequencies and phase positions and with known time intervals in certain time slots. The receiver carries out a series of time-shifted FFT operations over the time position where the synchronization frame is calculated to be. For each operation, a cross-correlation is carried out in the frequency plane of the output signal with the known frequency function of the synchronization frame. The correlation maximum is detected, and this determines the time slot which contains the synchronization frame, whereupon this is used as time base for the following data frames.
This invention is a circuit for generating a framing pattern consisting of a pseudo random shift register sequence. This circuit utilizes an extremely long framing pattern without either a large amount of memory or the need to receive a large number of bits in order to recognize the framing pattern. The use of lengthy framing patterns minimizes the chance of false framing caused by patterns in bit positions other than the framing bit position.
A low-power, spread spectrum synchronized communication system employing a satellite which continuously and iteratively re-transmits a PRS signal PRS.sub.m from a master earth station having a chip rate C.sub.m and a bit rate B.sub.m and comprising a plurality of ground stations each including a transmitter for transmitting a first PRS signal (PRS.sub.G) unique thereto and having a first chip rate C.sub.G and a first bit rate B.sub.G and a receiver for receiving and identifying PRS.sub.G after being returned by the satellite as PRS.sub.Gr with a chip rate C.sub.Gr and a bit rate B.sub.Gr. Also provided is a phase difference detector responsive to C.sub.m and C.sub.Gr to periodically produce a signal representative of the change of phase difference thereof and a frequency changing circuit responsive to such signal to change the chip rate C.sub.Gr by an amount which will cause the phase of C.sub.Gr to approach the phase of C.sub.m at a given rate.
