 |
Claims  |
|
|
What I claim as new and desire to secure by Letters Patent of the United
States is:
1. A cross-correlation analyser comprising: quantizing means for quantizing
a first random modulated signal and a second similarly modulated signal
having an unknown lapsed time interval from said first signal; variable
oscillator delay means for delaying said quantized first signal by a
succession of equal time delay increments to provide a series of delayed
quantized versions of said first signal in time overlapped relation with
said second quantized signal; a plurality of first comparison means each
receiving a respective said delayed first quantized signal of said series
and said second quantized signal, to simultaneously compare individual
ones of said first series of delayed quantized signals with said second
quantized signal; a plurality of counting means each connected to a
respective said comparison means, the individual average counting rate of
said counting means being a measure of the degree of coincidence between
the respective first and second quantized signals; signal overflow
detection means for determining which said counting means has the highest
rate; signal responsive servo means connecting said overflow means in
controlling relation with said variable oscillator to adjust said
oscillator delay increments in order to locate said highest counting rate
at a predetermined one of said counting means, and oscillator read-out
means to provide a function of said oscillator frequency as an inverse
function of said lapsed time interval.
2. The analyser as claimed in claim 1 including a fine mode circuit with
frequency multiplier, a related time shift register, second comparison
means connected to said overflow detection means to compare said highest
counting rate with a predetermined standard, control means connected to
said second comparison means and responsive to said standard being
exceeded to switch to said fine mode circuit, by connecting said frequency
multiplier with the circuit of said variable oscillator to significantly
diminish said time delay increments by a predetermined divisor, said
related shift register being serially connected to introduce a
corresponding compensating additional time delay to said quantized first
signal to compensate for the reduction in elapsed time of said first
series of delayed signals, so as to permit maintainance of said highest
counting rate at said predetermined counting means, in response to
adjustment by said oscillator servo means, whereby the sensitivity of the
analyser in response to adjustment of said oscillator and the accuracy of
said oscillator read-out means is correspondingly improved.
3. The analyser as claimed in claim 2 wherein said divisor has a value of
five.
4. The analyser as claimed in claim 2, wherein said control means is
responsive to said second comparison means, when operating in said fine
mode to switch the analyser for operation in a coarse mode of operation
upon said highest counting rate failing to achieve said predetermined
standard.
5. The analyser as claimed in claim 2 including error detection means to
identify the occurrence of first and second signals indicative of an
absence of correlation therebetween, during a counting cycle of said
overflow detection means, and signal rejection means responsive to an
unduly low level of correlation, to discard said cycle and to permit
retention of said analyser in operation with said fine mode circuit,
whereby premature reversion to the normal operational mode is delayed.
6. An analyser as claimed in claim 2 wherein said comparison means provide
determination of the ordinal position of said counting means having the
highest counting rate, said second comparison means having signal
diverting means connected thereto responsive to said counting rate below a
predetermined value indicative of a low degree of correspondence between
said quantized signals, to prevent an ordinal position error signal
passing to error signal summation, whereby the occurrence of a said signal
having a low probability of accuracy does not influence the mode of
operation of said analyser.
7. An analyser as claimed in claim 4 wherein said comparison means provide
determination of the ordinal position of said counting means having the
highest counting rate, said second comparison means having signal
diverting means connected thereto responsive to said counting rate below a
predetermined value indicative of a low degree of correspondence between
said quantized signals, to prevent an ordinal position error signal
passing to error signal summation, whereby the occurrence of a said signal
having a low probability of accuracy does not influence the mode of
operation of said analyser.
8. The method of determining the inherent time delay between a leading
incoming signal and a lagging incoming signal, comprising the steps of:
generating a series of delayed versions of the leading incoming signal to
provide a train of signals each delayed by a successive integer multiple
of a time delay interval covering a range which includes said inherent
delay; multiplying after each delay interval each said delayed signal with
the real time lagging signal to provide an output series proportional to
the respective degree of similiarity between said real signal and each
said delayed signal, averaging the products of each multiplication during
many delay intervals to provide a series of outputs each representing the
degree of cross correlation existing between the lagging signal and the
respective said delayed leading signal, comparing said outputs to
indentify the output having the maximum average value, noting the integer
number of time delay intervals producing said maximum average output, and
varying the frequency of said time delay intervals provided by a generator
to cause the number of time delay intervals required to produce the
maximum average output to correspond to a predetermined number of delay
intervals, wherein the frequency of said generator is an inverse function
of said delay time, and a direct function of the transport velocity of the
medium which caused the delay time between said leading and lagging
signals.
9. The method as claimed in claim 8 wherein control of said generator is
accomplished by: determining after each averaging process the magnitude
and direction of the difference between the number of time delay intervals
required to produce the maximum average output and said predetermined
number of time delay intervals, adjusting the frequency of said generator
stepwise by an amount corresponding to said difference thus changing the
duration of the time-delay intervals, reaveraging the products of said
multipliers to determine the number of new time-delay intervals required
to produce the maximum average output, repeating the steps of adjusting
and reaveraging continuously, whereby the frequency of said generator is
the algebraic sum of all preceeding correction steps, to provide integral
negative feedback control having zero offset error. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
This invention relates to a system for determining the time relationship
between two signals by means of cross-correlation analysis, and in
particular provides a cross-correlation apparatus suitable for use with a
fluid flowmeter.
Considerable use has been made and is being made of systems embodying cross
correlation techniques for determining the time delay relationship between
succeeding related signals modulated to a corresponding but not identical
pattern. One practical use of such a cross-correlation technique has been
to measure the velocity of flow of a liquid through a pipe between a pair
of spaced-apart stations transmitting ultrasonic signals diametrally
across the pipe, as shown in British Specification No. 1,398,381 June 18,
1975 Gritten et al. Modulation of the transmitted signals is effected by
flow disturbance patterns which travel with the flow. Thus the signal
modulation sensed at the downstream station may well have a characteristic
similarity to that previously received at the upstream station, without
however being identical, since significant values of unrelated signals are
inescapable. Known techniques of cross-correlation are used by applying
determinable time delays to the modulated signal from the upstream
station, comparing by multiplication with the downstream signal and
averaging to establish the degree of correlation between the signals. When
maximum correlation is observed it is indicative that the delay time
period which produces such correlation represents the time of passage of a
flow disturbance between the upstream and the downstream station, and
thereby represents a reciprocal function of the flow velocity in the pipe.
In some prior systems, the predominant practice has been to delay the
leading signal by a number of fixed time delay intervals and to infer the
characteristic delay between the leading and lagging signals by noting the
delay interval at which the greatest degree of correspondence exists
between the signals. The possible accuracy in determining the
characteristic delay is limited by the discrete nature of the delay
intervals, so that if the delay to be determined is near the minimum
measurable, the leading signal is delayed by only a few intervals and the
achievable accuracy is poor. For example, a range of actual delay times
lying between 4.5 and 5.5 delay intervals will all indicate maximum
correspondence at 5 delay intervals, causing a 20% uncertainty in the
inferred delay time. For flowmeter applications the required readout is in
terms of flow per unit time which is inversely proportional to delay time.
Hence a system in which the output is determined in terms of the number of
fixed delay intervals, requires an additional operation to compute the
reciprocal, an undersirable complication.
If the delay interval is made variable and the number of intervals is
fixed, as in the present invention, the readout can be derived from the
frequency of the oscillator which generates the variable delay interval,
which frequency is directly proportional to the flow per unit time,
avoiding the reciprocal computation. In other prior systems in which a
variable time delay interval is used, a limited number (for example 3) of
delayed versions of the leading signal are compared to determine the sign
of the error between the actual characteristic delay of the signals and
that indciated by the existing time delay interval. Limiting the number of
delayed versions reduces the cost of the circuitry required but restricts
the amount of information available to correct errors in the indicated
time interval, leading to longer response time and greater statistical
scatter in the measurement.
The present invention by utilizing digital large-scale integrated-circuits,
previously designed by others for the realization of a cross-correlation
analyser having fixed time delay intervals, in a manner which allows
operation with variable time delay and simultaneous calculation of the
cross-correlation function at many time delay intervals having a small
incremental differences (for example 1 in 160), provides in an economical
instrument the benefits of fast response, minimum statistical scatter, a
constant and negligibly small measurement uncertainty throughout its flow
range, and a frequency output which is a direct analogue of flow velocity
per unit time.
In accordance with the present invention there is provided a
cross-correlation system operating on analogue input signals digitally
quantized by first generating from the signals corresponding binary
signals the state of which changes with a change in polarity of the
corresponding analogue signals, having a variable frequency oscillator
which determines the instant at which the binary signals are sampled and
the duration of discrete time delay intervals applied to the signal
received from an upstream station, and a series of multipliers and
counters operating on the series of delayed upstream signals together with
the non-delayed sampled signal from a downstreamstation, such that a
condition of maximum correspondence between the pairs of delayed and
non-delayed signals is indicated by the overflow of one of the series of
counters, and a feedback system connected in controlling relationship with
the oscillator to vary the sampling and time delay intervals such that the
overflow indications is made to occur on the average in a chosen one of
the counters, which means to select alternative modes of operation based
on the degree of such correspondence, whereby in a coarse mode the
provided series of multipliers and counters covers a wide range of time
delay intervals and in a fine mode the same series of multipliers and
counters covers a more restricted range of delay intervals with a
corresponding reduction of the sampling interval and consequent increase
of the sampling frequency. Means are provided to maintain the time
required to determine the degree of correspondence substantially constant
and independent of the variable sampling time.
The selection of digitally quantized signals reduced to binary state
signals represents optimum simplification at the input or sensing end of
the apparatus, but is referred to generically as quantizing.
In a cross correlator as incorporate in the present system the
cross-correlation function is defined mathematically by the expression
##EQU1##
where R.sub.xy (.tau.) is the correlation function,
x and y are the two signals being analyzed
T is the time interval of the analysis and
.tau. is the delay time imposed on signal x to achieve correlation.
With x and y being random noise signals, that are related because some of
the noise components of y appeared in x at a time .tau..sub.d earlier,
R.sub.xy (.tau.) will have a maximum value when .tau. =.tau..sub.d. The
magnitude of R.sub.xy (.tau.) for other values of .tau. has significance
for the determination of the frequency and phase relationships between the
components of x and y, but for the purpose of measuring .tau..sub.d, only
the maximum of the function is of interest. With this restriction, certain
simplifications can be made in computing the function with the aim of
reducing the complexity of the apparatus while still maintaining an
adequate accuracy in the determination of .tau..sub.d and providing an
ability to follow sudden changes in its value which occur in practice.
In carrying out cross-correlation it is known that two analogue input
signals, x(t) and y(t) may be digitally quantized into binary form by
determining their polarity, which technique does not reside in the present
invention.
In the present invention, the quantized x(t) signal is delayed in an R
stage serial-in parallel-out shift register by a number of discrete time
intervals, each of size .DELTA.t. At the rth output of the shift register
the signal appears as x(t - r.multidot..DELTA.t), where r represents the
ordinal number of the output under consideration. The time intervals
.DELTA.t are controlled by a sampling pulse generator whose frequency can
be varied, consequently varying .DELTA.t. The R outputs of the register
are each associated with a simple binary multiplier which compares the
register output with the quantized y(t) signal during each time interval
.DELTA.t, and provides a logic 1 output during which .DELTA.t when x(t -
r.multidot..DELTA.t) and y(t) are in the same logic state. Each of the R
multipliers is connected to a digital counter having a capacity of N
counts, which counts pulses from an averaging clock during those sampling
intervals when the output of the associated multiplier is in the logic 1
state.
The probability, P.sub.r, that the output of the rth multiplier is in the
logic 1 state during any sampling interval depends upon the relationship
between its two binary input signals, which comprise the quantized
versions of y(t) and x(t - r.multidot..DELTA.t). If these two signals are
randomly related, P.sub.r = 0.5. If they are identical (perfectly
cross-correlated, P.sub.r = 1. When the two signals are related by a time
delay .tau..sub.d, the probability of correspondence is a maximum for that
multiplier r.sub.m for which .tau..sub.d =r.sub.m .multidot..DELTA.t and
will be designated, P.sub.m.
The time required for the rth counter to be filled to capacity if
N/.psi.P.sub.r where .psi. is the pulse rate of the averaging clock. This
time-to-fill function is independent of .DELTA.t but can vary over a 2:1
range depending upon the value of P.sub.r.
If all counters are reset to zero, the one associated with the multiplier
r.sub.m, having P.sub.m, the maximum value of P.sub.r, will fill first and
will represent the location of the peak of the cross-correlation pattern.
The ordinal position, r.sub.m of this counter is noted and the time delay
is determined as .tau..sub.d =r.sub.m .multidot..DELTA.t.
The number of pulses of the averaging pulse generator required to fill the
counter at position r.sub.m can be compared with the capacity N of the
counter, to determine P.sub.m for the correlation peak. The magnitude of
P.sub.m is used to indicate to the operator the suitability of the signals
x and y for his measurement purposes. It is also used to automatically
control the operating mode of the correlator and, at times, to reject
unsuitable signals, as will be explained.
Correlators in which the leading signal x(t) is delayed by a number of
fixed time intervals .DELTA.t cannot determine the time delay .tau. to a
greater precision than .+-..DELTA.t. Since .tau. is measured as n .DELTA.t
the possible error in
##EQU2##
When .tau. and hence n is small, this error can be inadmissibly large. To
overcome this problem, the present invention, using the relationship
.tau..sub.d =r.sub.m .multidot..DELTA.t, varies .DELTA.t to bring the
correlation peak to a chosen position r.sub.c in the total register R
where r.sub.c>> 1. This is accomplished by periodically determining the
identity of the overflowing counter r.sub.m, computing the magnitude and
sign of the error function r.sub.c -r.sub.m, integrating this error
function for form a control signal for the sampling pulse generator which
controls .DELTA.t, so that when the average of r.sub.c -r.sub.m is zero,
.DELTA.t is maintained constant.
That is to say, value of time delay .DELTA.t is adjusted to bring the
maximum of the function R.sub.xy (.tau..sub.d) into coincidence with a
predetermined counter r.sub.c, whereat r.sub.c =r.sub.m. The value of
frequency corresponding to the .DELTA.t value at which r.sub.c -r.sub.m =0
provides a continuous output directly proportional to a measured velocity
or directly related variable.
To minimize the total number R of multipliers and associated counters and
other circuit elements, while enabling .DELTA.t to be short so as to
utilize the high frequency components of the signals, a fine mode of
operation is provided which becomes automatically operable when r.sub.c
-r.sub.m is less than a predetermined value and the average value of
P.sub.m is sufficiently high. In this, the fine control mode, .DELTA.t is
reduced to a small fraction, such as 1/5, of its original value and the
ordinal position r.sub.c of the multiplier chosen as the desired peak
position is simultaneously increased by the corresponding multiple, such
as 5 times its original value, so that the product of
.DELTA.t.multidot.r.sub.c remains constant. The change in ordinal position
r.sub.c is obtained very simply by inserting before the input of the R
stage serial-in parallel-out shift register a serial-in serial-out shift
register having a suitable number of states ›such as (5-1)r.sub.c, if the
multiple chosen is 5!. The relationship between .DELTA.t and the frequency
of the sampling pulse generator is also adjusted by the same factor (5 in
this example) so that the frequency of the variable oscillator is not
affected when the fine mode is adopted.
When operating in the "fine-mode" a large and very rapid change of value of
time delay .tau. could exceed the rate at which .DELTA.t can change to
keep the peak position r.sub.m within the R stages equipped with
multipliers and counters. If this happens the factor R for all R stages
will decrease below the threshold level set for "fine-mode" operation. At
such occurrence the coarse mode is reverted to, the serial-in serial-out
shift register is switched out of circuit and .DELTA.t is changed until
r.sub.c -r.sub.m is again less than the predetermined value and
"fine-mode" operation automatically resumed.
An additional feature is optionally provided, which permits rejection of
error correction determinations which arise from sequences of input
signals having low correlateable content. It has been discovered that the
presence of correlateable components in typical signals from certain
flowmeter applications can vary widely in intervals of a few seconds. The
present invention determines the probability factor P.sub.m for each
cycle, i.e. a sequence of signals which fills one of the R counters. An
optional circuit is provided which, if P.sub.m is below a selectable
limit, will reject the computed error function r.sub.c -r.sub.m for that
cycle so as to avoid changing the oscillator frequency and thus to reduce
statistical disturbances of .DELTA.t due to random phenomena. This has
been found to measurably reduce the statistical scatter in the
determination of the time delay in certain applications.
Certain embodiment of the invention are described, reference being made to
the accompanying drawings, wherein;
FIG. 1 is a schematic arrangement of a process correlator in accordance
with the present invention; and
FIG. 2 is a timing diagram of the subject correlator giving indication of
the respective signal logic levels, so as to clarify the interelationship
of the pulses on the various lines.
To construct a correlator in accordance with the present disclosure it has
been found feasible to utilize digital large-scale integrated circuits
previously designed for carrying out a cross correlator system of others.
FIG. 1, comprising complementary FIGS. 1a and 1b schematically defines the
circuit diagram, while in FIG. 2 there is illustrated the related signal
levels appearing on the circuit conductors, being either a logic zero or a
logic 1 condition.
The apparatus shown in FIG. 1 includes a binary shift register 101
consisting of a large number (R) of identical binary storage stages 102
connected in series. For convenience only the first, second, (R-1)th and
Rth of the stages 102 are shown. Each stage 102 has a control terminal to
which is applied, via line 220, a train of sampling pulses having a period
of .DELTA.t seconds, and is operative so that changes of state of its
output (between logic 0 and logic 1 in either sense) occur only at the
ends of these pulses, the state assumed by the output of the stage at the
end of each pulse being the same as the state of the input of the stage at
the beginning of that pulse, such a storage stage may for example
conveniently be constituted by a master slave JK flip-flop.
The sampling pulses on line 220 are derived from the output of a variable
frequency oscillator 212 of frequency f, by digital counters 204 and 205.
Counter 204 produces one output pulse for each "d" input pulses (typically
d=400) and counter 205 produces one output pulse for each "e" input pulses
(typically e=5).
A switching means 201 is provided having two sections 201a and 201b which
operate simultaneously under control of controller means 238 which will be
described later. Switch 201b allows counter 205 to be selectively
interposed between the oscillator 212 and counter 204, thus the sampling
interval .DELTA.t =d.multidot.e / f seconds with switch 201b in the
position shown or .DELTA.t=d / f with switch 201b in the opposite
position.
Two identical samplers 104 and 105 are provided which are operative under
control of the sampling pulses from line 220 to provide binary output
signals whose state will change at the end of a sampling pulse if the
polarity of their input signal at the beginning of the sampling pulse is
different from its polarity at the beginning of the previous sampling
pulse. Samplers 104 and 105 may for example each consist of a simple
polarity detector followed by a binary storage stage similar to stage 102.
It will be that, if the sampling time-interval .DELTA.t is sufficiently
short, the outputs of samplers 104 and 105 will approximate to binary
signals which change state whenever the polarity of their respective input
signals change, and that the outputs of successive stages 102 of the
register 101 will be in the form of increasingly delayed versions of the
output of sampler 104.
The output of sampler 104 is applied to the input of the first of the
stages 102 via switch 201a. With switch 201a in the position shown the
value of the delay of the rth stage is equal to r.multidot..DELTA.t where
r represents the ordinal position of the stage in the register 101. With
switch 201a in the opposite position to that shown, a "w" stage shift
register 202 is interposed between the output of sampler 104 and the input
of the first of the stages 102. Register 202, under control of the
sampling pulses from line 220 which are applied to its shift input, delays
the output signals from sampler 104 by w additional sampling periods so
that r then represents the actual ordinal position plus 2, the number of
stages in shift register 202.
Each stage 102 of the register 101 has associated with it a channel
comprising an EXCLUSIVE OR gate 106, an inverter 107, and AND gate 108 and
a pulse counter 109, all of the channels being identical. In each channel
the output from the related stage 102 is connected to one input of the
gate 106, and the output of sampler 105 is connected to the other input of
gate 106. The output of gate 106 is applied to inverter 107, the output
from which is applied to one input of gate 108. The other input of gate
108 is connected to a counting pulse line 222. The output of gate 108 is
applied to the input of counter 109.
Each counter 109 has a counting capacity of N and is operative so that
starting from a condition of zero count, its output will be in the logic 0
state until the end of the Nth pulse applied to its input, when the output
will change to the logic 1 state and will remain in this state until the
zero count condition is restored by the application of a logic 1 signal
via line 223 to the reset input of the counter. The condition of the
counter 109 when its output is in the logic 1 state will subsequently be
referred to as the overload condition.
To meet the requirements of the available integrated circuits, the counting
pulses on the line 222 are synchronized with the sampling interval by
deriving them both from a common source, oscillator 212. This is
accomplished by the provision of: a pulse generator 207 which produces
pulses at a frequency .psi., a flip-flop 210 having a clock input fed from
generator 207 a reset input and a Q output, and AND gate 209 having two
inputs the first connected to the output of oscillator 212 and the second
connected to the Q output of flip-flop 210 and having an output connected
to line 222, and a counter 208 having an input connected to line 222 and
an output at which one pulse appears for each g input pulses said output
being connected to the reset input of flip flop 208.
This circuit will generate an approximately constant number of counting
pulses per second although the frequency of the source oscillator 212 from
which they are derived varies over a range exceeding 10:1. The circuit
operates as follows: Assume the Q output of flip-flop 210 is in the logic
1 state, the output of gate 209 will be a train of pulses at frequency f.
When g such pulse have appeared, counter 208 will reset the output of the
flip-flop to logic 0 where it will remain until the occurrence of the next
pulse from the averaging clock generator 207. Thus batches of g pulses at
a pulse rate of f per second are delivered to line 222 at an average rate
of g.multidot..psi. (i.e. g times frequency of the generator 207) which
rate is not dependent on f, the frequency of generator 212.
The action of the samplers, register, associated gates and counters in
measuring the time delay of a correlation peak will now be described:
During each interval .DELTA.t defined by the sampling pulses, each gate
106 and inverter 107 combination feeds a logic 1 to the related AND gate
108 when there is a coincidence between the existing output state of
sampler 105 and the output state of sampler 104, r.multidot..DELTA.t
seconds earlier in time. The probability of the existence of said
coincidence in the rth stage may be expressed as P.sub.r which is a
statistical function of the input signals x(t) and y(t) and of the time
delay r.multidot..DELTA.t incorporated in the quantized version of the
signal x(t-r.multidot..DELTA.t) which appears at the rth storage stage
102. If the signals have no correlatable content, P.sub.r will average 0.5
for all stages. If y(t)=x(x-.tau.), P.sub.r will equal 1 when
r.multidot..DELTA.t=.tau.. In practice 0.5
|
|
|
|
|
|
|
Description |
|
