A phase synchronizing circuit for use in a multi-level, multi-phase, superposition-modulating signal transmission system is disclosed. The circuit includes a voltage-controlled oscillator which is responsive to a phase error signal. The output of the voltage-controlled oscillator is supplied as the reference input to a phase-detecting circuit. First and second demodulator circuits receive the output of the phase-detecting circuit and detect the superposition modulated signal. A logic circuit processes the outputs of the demodulator circuits to produce a signal representing a phase difference between first and second modulated carrier waves. Control circuitry is responsive to the output of the logic circuit for controlling at least one of the phase variation and the amplitude variation on the phase error signal.
A demodulator for a composite PSK-PSK modulated signal having a 2.sup.n -phase main data signal and a 2-phase subdata signal including a frame signal, said demodulator comprising an orthogonal detector 21 producing two orthogonally demodulated signals P, Q, a subdata reproducing section 50 for phase-shifting the orthogonal signals and multiplying together the phase-shifted signals to reproduce the subdata signal, a lock-in phase discriminator 42 for detecting the frame synchronization, and a main data reproducing section 51 for phase-shifting and switching the orthogonal signals in response to the phase discriminator and the reproduced subdata signal to reproduce the main signal.
A multi-level, multi-phase, superposition-modulated signal is phase detected in a four-phase phase detector with the output from a voltage controlled oscillator (VC0). The P and Q outputs from the phase detector are supplied to a plurality of phase shifters and level discriminators to generate a plurality of digital signals corresponding to various phase positions of the received signal, and the P and Q signals are also supplied to demodulator and logic circuitry. Mutually orthogonal pairs of outputs from the level discriminators are frequency multiplied in Exclusive OR (EOR) gates, the outputs of which are selectively passed through a gate circuit in accordance with the phase position of the received signal determined by the output of the logic circuitry. A pair of mutually orthogonal demodulator outputs are also frequency multiplied by combination in a second EOR gate, and the output of the gate circuit is then frequency doubled by EOR combination with the output of the second EOR gate. This frequency-quadrupled signal is then supplied as the control voltage to the VCO.
An n (=8, 9)-valued polyphase modulation system having circuit construction for carrier regeneration in which not only correct phase demodulation is effected but also any AM components of the regenerated carrier wave are effectively compensated for and in which the decision circuit is adapted to produce a signal output having no phase ambiguity which is coupled to a .pi./4 phase modulator unit of the carrier generator to serve as a drive signal therefor.
An adaptive differential phase shift keyed (PSK) signal demodulator which optimally tracks changes in the symbol rate of the signal. An input signal is delayed by one symbol period by passing the signal through a charge coupled device (CCD) clocked by pulses phase locked to the symbol rate (F.sub.br) by a phase locked loop, the phase locked loop also outputting clock pulses at the symbol rate to strobe a symbol decision circuit. The CCD has L stages and is clocked at a rate L.multidot.F.sub.br. As the phase locked loop tracks changes in the symbol rate, the clock pulses are varied in rate so that the CCD delay is adaptively optimized for a given symbol rate. Digital tuning is provided by an adjustable divider circuit coupling the voltage controlled oscillator of the phase locked loop to the CCD, so that by digitally selecting the division ratio the demodulator is tuned to a different symbol rate.
