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Claims  |
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What is claimed is:
1. In a system having:
a clock generator for generating clock pulses,
an excutive computer having a bus system including a timing bus, an order
bus, a data bus, and a plurality of function units, one of the function
units having a set of selectable registers for storing instructions to be
read and processed sequentially during processing cycles, each consisting
of a given number of equal timing phases established by the clock
generator and having means for selecting a register in response to a
received address, said sets of registers storing the instructions for
performing a processing routine with a first of said registers storing the
first instruction of said processing routine, said function units being
connected to said timing bus for receiving timing signals, being connected
to said data bus to receive and/or transmit data, and being connected to
said order bus to receive and/or transmit instructions and/or addresses,
and,
a reserve computer for working in parallel synchronism with the executive
computer to perform the same processing routine, the reserve computer
having a timing bus, an order bus, a data bus, and a plurality of function
units, one of the function units having a set of selectable registers for
storing instructions to be read and processed sequentially during
processing cycles, each consisting of a given number of equal timing
phases established by the clock generator and having means for selecting a
register in reponse to a received address, said sets of registers storing
the instructions for performing a processing routine with a first of said
registers storing the first instruction of said processing routine, said
function units being connected to said timing bus for receiving timing
signals, being connected to said data bus to receive and/or transmit data,
and being connected to said order bus to receive and/or transmit
instructions and/or addresses;
the improvement comprising apparatus for controlling and initiating the
parallel synchronous operation of the computers on the same data, said
apparatus comprising, a unidirectional data transfer channel having an
input and an output, means for connecting said input to the data bus of
the executive computer, means for connecting said output to the data bus
of the reserve computer, said data transfer channel introducing a known
time delay in signals representing data transferred from the executive
computer to the reserve computer, said time delay being greater than one
of said timing phases, initial start means for generating a start signal
to indicate the start of cooperation between the two computers, executive
computer start means having an input and an output connected to the order
bus of the executive computer, means for connecting the input of said
executive computer start means to the initial start means, said executive
computer start means further having means responsive to the receipt of
said start signal at the input of said executive computer start means for
transmitting from the output of said executive computer start means the
address of said first of the registers of said set associated with the
executive computer to said one function unit of the executive computer,
time delay means for transmitting a delayed start signal from a time-delay
output after a period of time substantially equal to said known time delay
after the occurrence of the start signal, and reserve computer start means
having an input and an output connected to the order bus of the reserve
computer, means for connecting the input of said reserve computer start
means to the time delay output of said time delay means for receiving the
delayed start signal, said reserve computer start means further having
means responsive to the receipt of the delayed start signal for
transmitting from the output of said reserve computer start means the
address of said first of the registers of said set associated with the
reserve computer to said one function unit of the reserve computer, so
that the transfer of the address of said first register from said reserve
computer start means is delayed with respect to the transfer of the
address of said first register from said executive computer start means by
a time effectively equal to the time delay introduced by said data
transferring channel so that each computer processes the same data with
the same instructions.
2. Apparatus according to claim 1 wherein said time-delay means comprises a
delay line.
3. Apparatus according to claim 1 wherein said time delay means includes a
shift register connected to the clock generator for stepping said shift
register, the product of the period of the clock pulses and a number of
the register steps being substantially equal to the time delay introduced
by said data transfer channel.
4. Apparatus according to claim 1 further comprising means for comparing
the data transferred by said data transfer channel with the data on the
data bus for the reserve computer and means for generating an alarm when
the data are different.
5. The apparatus according to claim 1 wherein said initial start means
comprises a source of a primary start pulse, an interrupt unit
interconnected with one of the buses of the executive computer, said
interrupt unit being adapted to receive a primary start pulse to interrupt
the operation of the executive computer, and means for generating said
start signal, and wherein said means responsive to the receipt of said
start signal of both said executive computer start means and said reserve
computer start means respectively include a register for storing the
address of said first of the registers of the respective sets of
registers.
6. Apparatus according to claim 1 wherein said executive computer start
means further comprises a phase generator means having an input connected
to the clock generator and an output connected to the timing bus of the
executive computer for generating the timing phases of the processing
cycles of said instructions processed by the executive computer, said
reserve computer start means further comprises a phase generator means
having an input connected to the clock generator and an output connected
to the timing bus of the reserve computer for generating the timing phases
of the processing cycles of said instructions processed by the reserve
computer.
7. Apparatus according to claim 6 further comprising means responsive to
the start signal for activating the phase generator means of said
executive computer start means, and means responsive to the delayed start
signal for activating the phase generator means of said reserve computer
start means.
8. Apparatus according to claim 7 wherein said time delay means is a delay
line having an input connected to said initial start means and an output,
and means connecting said output to said means for activating the phase
generator means of said reserve computer start means.
9. Apparatus according to claim 6 wherein said time delay means is a shift
register which is connected to said initial start means and is shifted by
the clock generator and has a first output connected to said means for
activating the phase generator of said executive computer start means and
a second output, downstream from said first output, connected to said
means for activating the phase generator of said reserve computer start
means so that the activation of the phase generator of the reserve
computer start means occurs after the activation of the phase generator of
said executive computer start means.
10. Apparatus according to claim 1 wherein said means for connecting the
output of said data transfer channel to the data bus of the reserve
computer comprises transfer control means having a first input connected
to the output of said data transfer channel and an output connected to the
data bus of the reserve computer for controlling the passage of signals
from said data transfer channel to the data bus of the reserve computer.
11. Apparatus according to claim 10 wherein said transfer control means has
a second input connected to the data bus of the reserve computer and
further comprises means for selecting which of two inputs of the transfer
control means passes signals to the data bus of the reserve computer.
12. In a twin computer system timed by a common clock generator of clock
pulses and interconnectable by a channel means which introduces a time
delay in units of data traversing said channel means greater than a clock
pulse period, wherein first and second computers process, in parallel,
units of data from a plurality of operational units with the first of said
computers being the executive computer and the second the reserve
computer, and wherein said computers are identical and each comprises both
a first function unit and a second function unit interconnected by a bus
system including order and data buses, the method of initiating the
operation of both computers to process the same data comprising the steps
of starting the first computer to process units of data, starting the
second computer to process units of data a given period of time after the
starting of the first computer, and actively connecting unidirectionally
the data bus of the first computer to the data bus of the second computer
for a certain length of time whereby a unit of data being transferred from
the first function unit of the first computer to the second function unit
of the first computer is also transferred to the second function unit of
the second computer which corresponds to said second function unit of the
first computer, so that the second computer is initially loaded with units
of data being processed by the first computer, the given period of time
the second computer is started after the first computer being
substantially equal to the time required for a unit of data to be
transferred from the data bus of the first computer to the data bus of the
second computer. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
This invention pertains to computer control systems and more particularly
to those systems utilizing twin computers operating in
parallel-synchronous cooperation.
In real time systems such as stored program controlled telecommunication
systems it has been common to employ control computers using unified-bus
principles. Typically, in such systems the computer which controls the
telecommunication devices or units is in turn controlled by a clock
generator. Within the computer the operating units are all connected to a
common or unified bus. Typical unified-bus computers used in
telecommunication systems are the No. 2 ESS Call Processor whose block
diagram is shown on page 2634 of The Bell System Technical Journal of
October 1969, and the computer disclosed in U.S. Pat. No. 3,631,401 and
called a Direct Function Data Processor.
Such computers and particularly that of said patent have an order bus and a
data bus in addition to timing circuits. It is because of the bus
configuration that such computers can be easily modified, expanded or
modernized as new components become available. This flexibility is highly
desirable. More particularly, because a unified-bus system comprises a
number of parallel wires for transmission in parallel and digital form of
data (data bus), addresses and order in parallel (order bus) and to which
wires all the computer parts are connected, there is obtained a
modular-system principle with the function or operating units of the
computer being the modules. The function units are connected to the
unified-bus system in a uniform manner by uniform interfaces, for example
in the form of buffer registers accessable by encoding. By choosing
suitable modules there is obtained the most varying computer
constructions, such as minicomputers, microcomputers, calculators or
real-time computers to control simple or complicated processes.
The unified-bus modular system is also used when building real-time
controlled telecommunication systems. The demands for real-time
controlling of telecommunication processes often necessitate to
distinguish between fast and slow acting function units, i.e. to introduce
different bus systems for different data processing speeds and to provide
buffer units with the interface for constituting the connection means
between the bus systems. If the central function units which carry out the
computers own operations and the buffer units between the central and
peripheral units are constructed with very fast reacting logical
components such as TTL-(Transistor-Transistor-Logic)-circuits and are
connected to a central bus system, the properties of the central bus
system constitute a limit which must be observed in the determination of
the resulting data processing speed. The data transmission speed available
on a bus is namely influenced by the interface-number, i.e., the number of
connected function units, and by the physical length of the wires in the
bus system. A suitable limitation of the number of central parts
consequently results in optimum short processing cycles for data
processing instructions transferred via the central bus system and results
consequently in a very effective real-time controlling of the
telecommunication process.
Since transient phenomena arise in connection with a change of the logical
condition (changes in the states of the signals on the wires of the buses)
of the bus system phase division of the processing cycles in necessary,
and with the purpose to obtain the fastest possible data processing, the
frequency of the clock generator (the basic timing of the computer) is
chosen so high that the delay in time because of such transient phenomena
and such reaction times of the components is just about controlled. For
example, clock pulse frequencies of 20 MHz and processing cycles of 200 ns
are typical.
These delays inherent in unified-bus systems can cause problems.
Nevertheless, because of the modularity advantages of such systems, they
are used. However, attention must be paid to the properties of such a bus
system when designing processing cycles for the data processing
instructions and when connecting the computer to further means, for
example to a data transferring channel.
Generally there may be instructions of different types associated with
processing cycles consisting of different numbers of timing phases defined
by means of timing pulses generated by the clock generator. In a computer
provided with the unified-bus, data transfer instructions demand the
longest processing cycles because the bus system and two function units
are involved, the first one sending data and the other one receiving data.
Other instructions which require only one of the function units to carry
out a function demand usually shorter processing cycles.
The above-discussed systems however have low reliability in
telecommunication systems. A fault in the operation of the computer causes
a down-time of the telecommunication process. It is possible that the
down-time includes a period during which the computer sends nonsense to
the devices before the fault is discovered and the whole system is cut
off. The down-time includes further diagnostic time to localize the fault,
as well as to repair the computer and to restart the system. There are
known many methods for increasing the reliablity of a real-time system. At
page 57 of Design Of Real Time Computer Systems, by J. Martin published in
1967 by Prentice-Hall, Englewood Cliffs, N.J., there are shown many
examples of configurations using two computers. What in the present
application is called "parallel-synchronous co-operation" corresponds on
said page 57 to the so-called "twin-configuration". In particular, there
are two substantially identical computers A and B. Both computers A and B
receive the process data being processed identically. In the present
application, the computer which sends process data to the
telecommunication equipment is called the executive computer, while the
other of the two computers is called reserve computer. The results
obtained in processing by the computers are compared. If the results do
not agree, the control of the telecommunication equipment is interrupted.
A first down-time period exists until it is established which computer is
faulty. Then the fault-free computer continues to send process data to the
equipments. It is important to localize and repair the fault as soon as
possible because during the period for localization and repair the
reliability is the same as for a single computer system. After the
repairing of the faulty computer, the twin-configuration is renewed, the
repaired computer now being the reserve computer. However, the following
result comparisons are meaningless as long as the reserve computer is not
updated i.e., loaded with the same information being processed by the
executive computer. Thus it is known to allow a second down-time period
during which all updating is carried out.
SUMMARY OF THE INVENTION
It is an object of the invention to shorten the down-time of a dual or two
computer system after the discovery of a fault.
The down-time is shortened by carrying out updating during the operation of
the executive computer. For updating, the reserve computer is supplied not
only with the process data from the telecommunication devices, but also
with the results originated by the function units of the executive
computer. During updating, the function units of the reserve computer are
prevented from transmitting their results. After some time the results
generated by the reserve computer will be the same as the results
generated by the executive computer, i.e., the updating is finished
without the above-mentioned second down-time period. Of course, the
reliability during such updating is the same as for a single computer
system. A complete updating during the operation of the executive computer
is achieved by means of a data transferring channel undirected from the
data bus of the executive computer to the data bus of the reserve
computer. However, the use of the data transferring channel raises a
serious phase displacement problem because of, for example, the
transmission time across such channel as well as the times on the data
buses of both computers.
It is another object of the invention to compensate for such phase
displacement.
The compensation is obtained in accordance with the invention by providing
apparatus for starting the reserve computer a period of time after the
starting of the executive computer which is related to the time duration
of the phase displacement.
BRIEF DESCRIPTION OF THE DRAWING
The features and advantages of the invention will be apparent from the
following detailed description when read with the accompanying drawing
which shows apparatus for practicing the invention. In the drawing:
FIG. 1 is a block diagram of a telecommunication system using twin
computers;
FIG. 2 is a timing diagram for explaining the operation of the system of
FIG. 1;
FIGS. 3 to 5 show three different embodiments of the invention wherein an
executive computer is connected via a data transfer channel to a reserve
computer wherein both computers are started by a common start pulse
source.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
In FIG. 1 there is shown a stored-program controlled telecommunication
system comprising a plurality of telecommunication equipments TES which
feed state information in parallel to reserve computer R and executive
computer E via the lines DI and which receive control data via lines DOE
from executive computer E. Note lines DOR connected reserve computer R to
the telecommunications equipment, but since the reserve computer does not
control the equipment it does not send control signals thereto. The
computers are for all purposes identical and simultaneously and
synchronously process the same data under control of clock generator CG
and start pulse source SP. The computers are of the unified bus type
wherein the function units FU of the computer are all connected in
parallel to unified bus structure UB. For example, one can use either of
the above-mentioned computers. While the processing is going on a
comparator KM compares the results from both computers. Whenever the
results disagree comparator KM emits a signal to alarm AL for causing the
shut-down of both computers. Error locating routines are then performed to
determine which of the computers is faulty. Heretofore, once it was
determined which computer broke down, the fault-free computer, say
computer E, was restarted to control the system via lines DOE while the
faulty computer was repaired. When the faulty computer was repaired, the
system was shut down and both computers loaded with the same data and
restarted. This second shut down is undesirable.
However, according to the invention the second down time for updating the
reserve computer is not necessary. In particular, once the fault is
localized the fault-free computer, say computer E, starts controlling the
system via lines DOE while the faulty computer say computer R is repaired.
When the faulty computer is repaired its bus system is connected via data
transfer channel DCH to the bus system of the operating executive computer
E and the reserve computer is started so that the data in the function
units of the executive computer E can be loaded into the corresponding
function units of reserve computer R. However, it should be noted that
there is a known time delay in data travelling from the bus system of one
computer via the data transfer channel DCH to the other computer. The
amount of this delay is known because once the system is installed the
actual delay is measured. Thus, the reserve computer is started at a time
so that proper (identical) phasing is present in both computer. (Note at
no time does the reserve computer R issue controls to equipments TES. It
only does so when it is the executive computer).
The timing effects will become apparent from a study of FIG. 2. FIG. 2
shows timing diagrams, I, for the timing pulses produced by the clock
generator CG, and II for the processing cycles associated with a number of
subsequent instructions processed by the executive computer. Each
processing cycle consists, according to the embodiments disclosed, of four
timing phases a to d. Timing diagram II shows the relations existing on
the bus system. There is a certain inevitable phase displacement between
the timing pulses and the timing phases. It is assumed that processing
cycle 6 is associated with a data transfer instruction. According to the
disclosed embodiments, the receiving function unit receives the
transported data during the last timing phase 7 of said processing cycle
6.
Since to achieve synchronization clock generator CG also times the reserve
computer the timing phases have equal lengths for both computers and the
results produced by both computers in corresponding timing phases are
compared. The timing diagram III of FIG. 2 shows processing cycles
processed by the reserve computer which correspond to the processing
cycles shown in diagram II. The computers are assumed to produce their
results in synchronism without any phase displacement. Thus, in diagram
III, processing cycle 9 including timing phase 10 corresponds to the
processing cycle 6 and the timing phase 7 of diagram II. Using the
unified-bus principle, it is convenient to connect the comparator means to
the both bus systems, however in a manner which does not cause a phase
displacement at the inputs of the comparator means which exceeds the
length of a timing phase. The timing diagrams IV and V of FIG. 2 show
examples according to which it takes the time periods 11 and 12 for
transferring the logical states of the bus systems obtained during said
timing phases 7 and 10, to the inputs of the comparator means. A correct
comparison process is possible because the periods 11 and 12 are
substantially equal. It is obvious that by means of modified periods 11
and 12, it would be possible to compensate an eventual existing phase
displacement between the timing phases 7 and 10.
For updating, the reserve computer R is supplied not only with the process
data from the telecommunication equipment TES but also with the results
originated by the function units of the executive computer E. During
updating, the function units of the reserve computer R are prevented from
sending their results. After some time the results generated by the
reserve computer R will be equal to the results generated by the executive
computer, i.e. the updating is finished without said second down-time
period. A complete updating during the work of the executive computer E is
achieved by means of a data transfer channel DCH unidirected from the data
bus of the executive computer to the data bus of the reserve computer. The
use of the data transfer channel raises a serious phase displacement
problem. The timing diagram VI of FIG. 2 shows that it takes the time
period 13 for transferring the logical states obtained during the timing
phase 7 from the data bus of the executive computer E through the data
transferring channel to the data bus of the reserve computer R which takes
the respective logical state during a displaced timing phase 14. As it is
understood from the above explanations, a correct updating is only
achieved if said timing phase 14 coincides with the timing phase 10.
For this reason, the system comprises start pulse source SP which initiates
the start of the reserve computer R in relation to the start of the
executive computer with a time-delay corresponding to such time period 13.
Consequently, the timing diagram III comprising the processing cycles
processed by the reserve computer has to be replaced by the timing diagram
VII. The result from the instruction processed by the executive computer E
during the processing cycle 6 is received not only in the addressed
function unit of the executive computer during the timing phase 7, but
when updating is going on also during the timing phase 14 in the
corresponding function unit of the reserve computer R. Said corresponding
function unit is addressed by means of the corresponding instruction which
is processed by the reserve computer during a processing cycle 15 which
corresponds to the processing cycle 6 due to the start of the reserve
computer delayed by a delay time 16 effectively equal to said time period
13.
Thus, correct comparison according to the invention is obtained if the
comparator inputs are connected to the output of the data transfer channel
and to the data bus of the reserve computer.
It should be noted that the system of FIG. 1 has been simplified. In
particular, there is another data transfer channel connecting the two
computers in the opposite direction, and with the inputs of the comparator
KM connected to the output of the other channel and the bus of the other
computer. This second channel and sets of inputs is used only when the
computers switch roles of executive and reserve. This second channel and
comparator are not shown since once the executive and reserve computers
have been established they perform no function.
The three embodiments of FIGS. 3, 4 and 5 show the controls of a
telecommunication system which include the executive computer E and the
reserve computer R. In each of the embodiments there is a common clock
generator CG. There are function units FUe, FUr, included in the executive
computer E and the reserve computer R respectively. These function units
are interconnected by means of bus systems consisting of a data bus dbe
and dbr, an order bus obe and obr, and a timing bus tbe and tbr,
respectively. Further there is indicated that each of the computers
comprises an instruction register sequence IRSe and IRSr, respectively,
which consists of a number of registers storing instructions which are
read out to the order bus in turn or in another prescribed sequence
because of, for example, a jump instruction. One of the instruction
registers, labelled with BIRe and BIRr, respectively, is a beginning
instruction register which stores an instruction by which the operation of
the computer is initiated in an absolutely determined manner. This
beginning instruction register is selected with a start jump instruction
transferred on the respective order bus. The timing phases of the
respective computer during the following co-operation of the computers are
fixed by the processing cycle of the start jump instruction, as will be
described below. Using jump instructions forms part of a generally known
computer technique and the processing manner of the jump instructions does
not affect the inventive idea more than what has been explained in the
beginning in connection with the processing of instructions by means of a
unified-bus-system connected to the function units.
The proposed apparatus according to the invention to facilitate the
co-operation of the unified-bus-computers comprises according to all three
embodiments as main parts a data transfer channel DCH and a start pulse
source SP provided with at least one delay element.
The data transfer channel DCH is connected unidirectionally from the
executive computer E to the reserve computer R and is used for the
co-operation between the computers, for example, for the updating of the
reserve computer R which is based on the data which during the executive
work are transferred on the data bus dbe of the executive computer E and
which via the channel DCH are transferred to the data bus dbr of the
reserve computer, i.e. without on the whole disturbing the real-time
controlling of the executive computer E. As appeared from the introductory
explanations, the function units are placed in a computer constructed
according to the unified-bus-system so that the physical dimensions of the
bus system are as small as possible. However, for a parallel operation of
two computers there are distances that, for example, for a symmetrical
transmission upon data transfer between the bus systems require that the
data transfer channel include in relation to a data bus double lengths of
wires, and also pulse amplifiers and pulse regenerators. The construction
of the data transfer channel is indicated on the figures only principally
since many constructions are usable. By way of example in each of the
FIGS. 3, 4 and 5 the data transfer channel has an input indicated by
amplifier DCHI connected by cable DCHC to an output indicated by amplifier
DCHO. However, it must be observed that all solutions impose on the
transferred data a time-delay which exceeds one period length of the
timing pulses generated (one timing phase) in clock generator CG which is
common to both computers.
During the updating, faulty data are produced by the reserve computer R
which must not be sent to an addressed function unit FUr. Therefore a
control memory CM is provided in the data transfer channel in order to
record a transfer state in a manual or automatic manner. The control
memory CM controls a transfer logic means TL which during a supplied
transfer state ts opens the transfer channel and prevents a transport of
faulty data. In the embodiments of FIGS. 3 and 5 the data bus dbr of the
reserve computer R is divided into a receiving part through which data are
transferred to one of the function units and a sending part through which
data are transferred from one of the function units. With the aid of a
first gate means G1 belonging to the transfer logic means TL such data bus
parts are interconnected and disconnected, respectively, in dependence on
a present normal operation of the reserve computer R and a transfer state
supplied by the control memory respectively. Furthermore the transfer
logic means TL connects by the aid of a second gate means G2 during
updating the receiving part to the data bus dbe of the executive computer
E to the receiving part of the reserve computer R. In such manner the
logic state of the data bus dbe is transferred during the processing
cycles to addressed function units of both computers.
In the embodiment according to FIG. 4 there is recorded a transfer state
not generally for the whole system, but separately for each of the
function units of the computers. In this case the second gate means G2 of
the transfer logic means is activated to open the data transfer path from
the executive computer E to the reserve computer R by the aid of a gate G
of the interface of the respective function unit. (Note in FIG. 4 that the
function unit FUr is shown in more detail than other function units.
However, the corresponding function FUe is exactly the same.) The
activating conditions of gate G are that a sending decoder SDEC has
recognized the addressing of the respective function unit for data
sending, the addressing being carried out via the order bus obr of the
computer, and that a transfer state ts is recorded in the conrol memory CM
of the function unit. This control memory CM is provided either instead of
or in addition to the above mentioned common control memory in the data
transfer channel DCH. Instead of a division of the data bus of the reserve
computer R into a receiving and a sending part and instead of a first gate
means of the transfer logic means there is used in this case in the
reserve computer R a sending gate means SG included in the interface of
the respective function unit. Sending gate means SG has one of its inputs
connected to the control memory CM of the function unit for manual or
automatic recording of the transfer state ts of the function unit. Because
of a recorded transferring state, sending of the data of the reserve
computer R is prevented while a recorded transfer state in one of the
function units of the executive computer E does not influence the data
sending of the executive computer E.
For the sake of clearness there is shown in FIG. 4 only one interface which
belongs to the bus system of the reserve computer R and which comprises an
interface-register REG, a receiving decoder RDEC and a receiving gate
means RG as well as gate G, control memory CM, sending decoder SDEC and
said sending gate means SG. Via the timing bus tbr of the bus system the
sending and receiving gate means respectively are controlled so that an
activation is obtained only during the timing phases intended for sending
and receiving. Data sending from the interface register via the sending
gate means SG to the data bus dbr of the bus system and data receiving
from the data bus of the bus system via the receiving gate means RG to the
interface register, respectively, takes place if the sending decoder SDEC
and receiving decoder RDEC, respectively, connected to the order bus obr
of the bus system recognize the addressing of the function unit for data
sending and data receiving, respectively, and activates one of the inputs
of the sending and receiving gate means, respectively.
The start pulse source SP comprises an interrupt signal unit IU and start
devices SDe and SDr for starting the associated computers E, R,
respectively. In the figures the interrupt signal unit IU is shown as an
added function unit, which in the usual manner comprises an interface
connected to the bus system of the executive computer. However, this does
not mean that the impedance load of the bus system is further increased,
since the interrupt signal unit is in reality included in an interrupt
unit of the computers which is not shown on the figures for the sake of
clearness. Each real-time computer for controlling a telecommunication
system is provided with such an interrupt unit known per se for receiving
incoming interrupt signals, to establish orders of priority and to supply
for each priority change a jump instruction which in the instruction
register sequence selects a beginning instruction associated to the
respective priority level.
In a system consisting of an executive computer and a reserve computer a
primary start pulse ps for the start of the parallel-synchronous operation
causes such an interrupt signal in each of the computers. To explain the
principle initiation of the start process for the parallel work of the
computers there is shown in the figures a flip-flop F, a calling device CD
and a decoder DEC. Flip-flop F is by the primary start pulse ps put to the
first stable state a by the aid of which the calling device is activated.
The instruction register sequence includes a register which is selected
regularly and stores an instruction to transfer eventual interrupt signals
of the interrupt unit. An interrupt signal obtained from calling device CD
is given a priority in the executive computer E, for example, so that when
a real-time controlling instruction which is in progress is finished an
instruction register is selected which contains an instruction to transfer
a coded ready-signal for a co-operation start to the interrupt signal unit
whose decoder DEC converts the ready-signal to a secondary start pulse ss,
which sets said flip-flop F to the second stable state b. Accordingly
without determining definite construction elements, the task of the
interrupt signal unit consists in, upon activation by a primary start
pulse ps, interrupting the executive work in progress and generating a
secondary start pulse ps for the parallel operation of the computers. If
the example mentioned in the beginning is used, i.e. that a processing
cycle for an instruction comprises four timing phases and that a function
unit addressed for data reception registers sent data during the last
timing phase of the processing cycle, the secondary start pulse is
obtained on the output of the interrupt signal unit during the fourth
timing phase in the processing cycle for the instruction to transfer the
ready-signal.
In other words, periodically a specific register BIRe of function FUe which
contains the instruction register sequence IRSe is periodically read. The
contents of that register are fed via the order lines obc to interrogate
the calling device CD for its receipt of a signal from flip-flop F in
response to a ps signal. If such signal is present the calling device CD
sends another signal via data lines dbe to the function unit containing
the instruction register sequence IRSe which instructs another function
unit to send via data bus dbe a start code to decode DEC.
The start devices SDe and SDr included in the star | | |
