 |
Description  |
|
|
BACKGROUND OF THE INVENTION
This invention relates to data processing systems and more particularly, to
data processing display systems including one or more display devices each
capable of displaying a desired image.
Prior art processing display systems are characterized by special purpose
memories which in the aggregate define a character generator. Typical
display devices are of the raster-scanned type, such as CRT-TV tubes. A
character to be formed at a location on the display screen is defined by a
matrix of selectively energizable points arranged in a plurality of
vertically oriented scan lines. As is conventional, a scanning beam scans
from left to right, one scan line at a time, until an entire "page" is
displayed, and then returns to the top scan line in order to "refresh" the
image on the screen. Typically, the image is refreshed 30 times per
second.
It is a characteristic of prior art systems that characters are definable
only in fixed "blocks" on the display screen, each block containing the
requisite matrix of energizable points. As is conventional, a display list
memory contains the character data to be displayed in the form of a
plurality of ASCII coded words each defining a particular character
element. A predetermined number of words in the display list memory define
each text line to be displayed. Each ASCII coded word from the display
list memory is forwarded to a separate font memory along with a signal
indicating a scan line number. For example, there may be eight scan lines
in the matrix for each character which then could be 8 .times. 8. Thus,
the scan line number signal could be a 3-bit code. The font memory
contains a plurality of words each representing the desired bit
configuration for each scan line of a particular character. It is the
output of the font memory that is supplied to the display controller for
transmittal in bit-serial format to the display device. The words of the
font memory are traditionally supplied directly one at a time to the
display controller. Other prior data processing display systems, such as
that disclosed in U.S. Pat. No. 3,895,357, store a predetermined number of
the font memory words, such predetermined number defining a small band of
the picture to be displayed, into a partial raster assembly store. Again,
however, special purpose memories are employed.
The main problem with these prior art "character generator" type display
systems is that they are generally limited to forming characters only, and
only on specifically predetermined portions or "blocks" of the display
screen. They do not have a "graphics" capability, i.e. the ability to draw
relatively high resolution lines and curves unrelated to the conventional
alphanumeric characters. U.S. Pat. No. 3,716,842 discloses a data
processing display systems that does have a graphics capability. However,
the system is relatively complex from a hardware standpoint in requiring,
again, special purpose memories.
It would be desirable, therefore, to provide a data processing display
system having the attributes of simplicity and generality, i.e. simplicity
in a hardware sense such as by avoiding special purpose memories, and
generality in a display capability sense such as being virtually unlimited
as to the nature and location of data displayed on the display thereby
providing a graphics capability.
SUMMARY OF THE INVENTION
In furtherance of this desirability, a data processing display system in
accordance with the present invention comprises a display device capable
of displaying a desired image, said display device including a plurality
of points each capable of being selectively illuminated; a main memory
storage device including a plurality of addressable storage locations,
each location capable of storing a multi-bit display word therein, at
least some of said addressable storage locations including in the
aggregate a number of display bits at least equal to said plurality of
points of said display device whereby a display bit map of said desired
image is capable of being stored and defined in said at least some
addressable storage locations; a display controller connected to said
display device and responsive to predetermined instructions for
controlling the illumination of said plurality of points of said display
device in accordance with said bit map stored in said main memory storage
device; a central processing unit including means for supplying said
predetermined instructions to said display controller, and means for
addressing the storage locations of said main memory storage device; and a
main data transfer bus connected to said main memory storage device, said
central processing unit and said display controller, said main data
transfer bus capable of transmitting the words stored in said at least
some addressable storage locations of said main memory storage device to
said display controller in order for said bit map to be displayed on said
display device.
Since every single point capable of being illuminated on the display device
has a corresponding bit location in the main memory storage device, the
central processing unit can easily access and manipulate the display data
in the same manner as with any other type of data normally stored in main
memory. This feature embraces the data processing display system of the
present invention with the desired attributes of simplicity and
generality, as those terms have been defined above.
These and other aspects and advantages of the present invention will be
more completely described below with reference to the accompanying
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram representation of an exemplary data processing
display system of the present invention;
FIG. 2 is a schematic block diagram representation of the control section
of the CPU depicted in FIG. 1;
FIG. 3 is a more detailed block diagram representation of the instruction
register and decoders depicted in FIG. 2.
FIG. 4 is a schematic block diagram representation of the data section of
the CPU and the main memory depicted in FIG. 1;
FIG. 5 is a representation of the different storage sections of the main
memory store depicted in FIG. 4;
FIG. 6 is a block diagram representation of a portion of the display
controller depicted in FIG. 1;
FIG. 7 is a block diagram representation of another portion of the display
controller depicted in FIG. 1;
FIG. 8 is a schematic drawing of logic elements which constitute portions
of the display controller as shown in FIG. 6;
FIG. 9 is a schematic drawing of additional portions of the display
controller as depicted in FIG. 6; and
FIG. 10 is a schematic drawing of the control logic of the display
controller as shown in FIG. 6.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 1, a data processing display system of the present
invention is shown. The system includes a central processing unit (CPU) 10
that is comprised of a data section 12 and a control section 14. The
system also includes a main memory 16 to be described below and a
plurality of input-output (I/O) controllers 18, e.g., "M" I/O controllers
designated 18.sub.(1) through 18.sub.(M). Each of the I/O controllers 18
is connected to a respective one of a plurality of I/O devices 20 for
controlling same. At least one of the I/O controllers 18, e.g. controller
18.sub.(1), is a display controller for controlling a display device
20.sub.(1). Examples of other typical I/O devices that may be employed as
I/O devices 20 in the system of FIG. 1 are disk drives, keyboards and
cursor control devices (sometimes each referred to as a "mouse"). The
depiction of only one display controller 18.sub.(1) and associated display
device 20.sub.(1) is, of course, only exemplary.
Information is transferred to and from the data section 12 of the CPU 10 by
means of a main data transfer bus 22. The information is desirably
transferred in bit-parallel format. Typical CPU's are designed to operate
in 8-bit or 16-bit format, i.e., 8-bit or 16-bit quantities are
transferred to and from the data section 12 along the bus 22, which would
then be comprised of either at least eight or at least sixteen parallel
lines. Information may be transferred on the data bus 22 between the main
memory 16 and the data section 12, between the I/O controllers 18 and the
data section 12, as well as between each of the I/O controllers 18 and the
main memory 16.
Each of the I/O controllers 18, including the display controller
18.sub.(1), is capable of generating one or more task request signals in
the form of "wake-up" commands whenever the particular controller 18
requires one or more services to be performed by the CPU 10. The specific
nature of three wakeup-task request signals that are preferably generated
by the display controller 18.sub.(1) will be described in more detail
below. The wakeup-task request signals from the controllers 18 are applied
on respective lines 24.sub.(1) -24.sub.(N). The three wakeup-task requests
from the display controller 18.sub.(1), arbitrarily designated
wakeup-tasks 1-3, are applied on lines 24.sub.(1) -24.sub.(3) to the
control section 14 of the CPU 10. In order for each controller 18 to be
informed when the CPU 10 is executing instructions relating to the
requested service, the control section 14 includes means to be described
below for applying a "task-active" status signal back to the controller.
These task-active status signals are applied on lines 26 from the control
section 14 to the controllers 18, as shown in FIG. 1. There are three
task-active lines associated with the display controller 18.sub.(1), i.e.
task 1 active on line 26.sub.(1), task 2 active on line 26.sub.(2) and
task 3 active on line 26.sub.(3).
Reference is now had to FIG. 2 where the control section 14 of the CPU 10
will be described. At the outset, it must be stated generally that the
control section 14 applies instructions to the data section for execution
thereby. Additionally instructions are applied to the various I/O
controllers 18 for execution thereby. The instructions are forwarded in
accordance with a particular sequence or routine to be carried out and
identified with a particular task to be serviced. The control section 14
includes means to be described below for determining which of a plurality
of wakeup-task request signals that may have been applied to the control
section 14 has the highest current priority value. More specifically, each
of the plurality of tasks to be serviced is preassigned a unique priority
value. Thus, performing a requested service for the display controller
18.sub.(1) may be of higher priority than performing a requested service
for I/O controller 18.sub.(M). The control section 14 then forwards
instructions associated with the highest current task to be serviced to
the data section 12 and respective I/O controller 18 for execution.
Referring now in more detail to FIG. 2, the control section 14 includes a
priority encoder 28 which has task request inputs connected to the N task
request lines 24. As explained above, wakeup-task request signals for task
1-N are provided from the I/O controllers 18. Additionally, a wakeup-task
request signal for task 0, which requests servicing the main program, is
always present, as will be explained in more detail below. The priority
encoder 28 includes circuitry (not shown) for generating a multi-bit
control signal on a respective plurality of lines 30 (only one shown)
related to the highest priority wakeup-task request signal currently
applied as an input to the encoder 28. The priority encoder 28 includes a
further input for receiving a RESET signal on a line 32 from an initialize
circuit 34 to be described in more detail below.
Now then, the control signal developed on lines 30 is applied to respective
inputs of a current task register 36 which responds to such control signal
for generating a multi-bit address signal that is applied in bit-parallel
format on a respective plurality of lines 38 from the register 36 to
respective inputs of an address memory 40. The address memory 40 includes
a plurality of storage locations, preferably defined by a respective
plurality of multi-bit registers (not shown). There are preferably N such
registers included in the address memory 40, each one being addressed by a
unique multi-bit code defined by the address signal applied thereto from
the current-task register 36 on lines 38.
Each one of the N registers in the address memory 40 is associated with a
respective one of the N tasks to be performed, as defined above. In
actuality, each of the address memory registers is capable of storing the
next address of an executable microinstruction stored in a
microinstruction memory 42. In this respect, each of the N address memory
registers may be thought of as a program counter for its respective task
to be serviced relative to the corresponding microinstruction routine
stored in the instruction memory 42.
Each instruction stored in the memory 42 is accessed in response to a
corresponding address signal applied on address lines 44 from the address
memory 40. Each instruction includes an instruction field preferably
comprised of twenty-two bits, and a next-address field preferably
comprised of ten bits. The specific constitution of the 22-bit instruction
field will be described in more detail below in connection with FIG. 3.
The instruction field is loaded into an instruction register 46 on lines
48 and is then applied through appropriate decoders 52 (also to be
described in more detail below in connection with FIG. 3) to the data
section 12 of the CPU. Certain of these decoded instructions are also
forwarded to the display controller 18.sub.(1), as will be discussed below
in connection with FIGS. 3 and 4. The next-address field is fed back on
lines 50 to the currently addressed register in the address memory 40. In
this manner, each of the N registers in the memory 40 will always contain
the address of the next microinstruction stored in the instruction memory
42 to be executed in accordance with the particular task to be serviced.
A portion of the twenty-two bit instruction field of each microinstruction
may be dedicated to various special functions, some of which are applied
on control lines 47 to respective ones of the I/O controllers 18 for
controlling same, and some of which are applied on control lines 49 to
address modifier circuits 56 (to be described below) for branching. In
accordance with the preferred embodiment, there is a four-bit special
function "sub-field" in the instruction field of each microinstruction
(hereinafter referred to as the "F1" sub-field), wherein two of the 16
four-bit codes capable of being defined (e.g. F1=2, F1=3) are respectively
representative of "TASK" and "BLOCK" functions. A TASK signal component of
an accessed instruction, upon being decoded by an appropriate one of the
decoders 52, is applied on a line 54 to the current task register register
36 for enabling same to load an address signal, representing the current
highest priority task requesting service. This address signal is then
applied to the address memory 40. A decoded BLOCK signal is applied on a
line 55 to the current task register 36 for disabling same.
It will be appreciated that a TASK signal can be presented in any desired
microinstruction during any routine to be executed. Normally, a TASK
signal would be generated at least once during each microinstruction
routine in order to enable any higher priority task awaiting service to
interrupt the current routine in order to be serviced by the CPU 10. If a
particular task to be serviced has a microinstruction routine that carries
out a plurality of different functions that can be independently serviced,
then a TASK signal would normally be written into the last
microinstruction of each segment of the routine identified with a
particular one of such functions.
Continuing with a description of FIG. 2, the control section 14 of the CPU
10 further includes conventional address modifier circuits 56 which, in a
known manner, are responsive to instructions on control lines 49 for
modifying the next-address signal being fed back on lines 50 from the
instruction memory 42 to the address memory 40. As is conventional, such
address modifiers are used for branching. The specific nature of the
address modifier 56 forms no part of the present invention and thus shall
not be described in detail.
The multi-bit address signal developed at the output of the current task
register 36, in addition to being applied to the address memory 40 on
lines 38, is also applied on lines 58 to a task-active decoder 60. The
decoder 60 responds to the address signal output of the register 36 and
generates one of the N TASK-ACTIVE signals alluded to earlier on its
respective line 26, dependent upon the current highest priority task to be
serviced. The decoder 60 includes a delay circuit for delaying the
application of a TASK-ACTIVE signal to the respective I/O controller 18 by
one clock cycle of the processor. In this manner, the appropriate
TASK-ACTIVE signal will be generated at a time corresponding to the
execution of instructions related to the task being serviced.
The control section 14 as shown in FIG. 2 also includes a clock generator
62 for generating appropriate CLOCK signals for application to the
current-task register 36 on a line 64, the task-active decoder 60 on a
line 66, the address memory 40 on a line 68, and the initialization
circuit 34 on a line 69.
Still referring to FIG. 2, the initialization circuit 34 is responsive to a
START signal generated when the system is turned on by the operator. Upon
receipt of the START signal, conventional circuitry in the circuit 34
causes a RESET signal to be generated which is applied to the priority
encoder 28 on line 32, to the current task register 36 on a line 70, to
the task-active decoder 60 on a line 72, to the instruction memory 42 on a
line 74, to the instruction register 46 and decoders 52 on a line 76, and
to the address modifier 56 on a line 78. Upon receipt of a RESET signal,
these various components of the control section 14 are reset.
The initialization circuit 14, in response to a START signal, also
generates a multi-bit initialization address signal on a respective
plurality of lines 80. In a preferred embodiment of the invention, "N"
equals 16 and thus the initialization address signal is a four-bit signal
that is initially zero, i.e., 0000, and is incremented by one at the rate
of the CLOCK signal pulses applied on line 69. The RESET signal is
maintained for sixteen cycles, i.e. sixteen CLOCK signal pulses, at which
time the initialization address on lines 80 will increment from zero
(0000) to fifteen (1111). As will be described below, the address signal
output of the current task register 36 during initialization is identical
to the initialization address signal. During initialization, the address
signal output of the current task register 36 is applied through an
AND-gate 82, which is enabled by a RESET signal from the initialization
circuit 34, to the address memory 40. In this manner, the address signal
(0000) will be loaded into register number zero in the address memory 40,
the address signal one (0000) into register number one, and so on. This
process initializes the address memory by setting the various registers
therein at their respective starting values.
Further details of the control section 14 of the CPU 10 may be had through
a review of copending U.S. application Ser. No. 769,254 filed on Feb. 16,
1977 as a continuation of now abandoned U.S. application Ser. No. 518,679
filed on Oct. 29, 1974 by Charles P. Thacker for TASK HANDLING IN A
MICRO-PROGRAMMED DEVICE and assigned to the assignee of the present
invention, both such applications being hereby incorporated by reference.
Referring now to FIG. 4, the basic elements of the data section 12 of the
CPU 10 are a register file 102, T register 106, L register 110, memory
address register (MAR) 114, and instruction register 116. The registers
106, 110, 114 and 116 are connected to the register file 102 and to an
arithmetic and logic unit (ALU) 120 by means of the main data transfer bus
22, which is desirably 16 bits in width.
Data is typically put onto the bus 22 from the register file 102 which is
preferably implemented by a group of 32 registers whose contents are read
or loaded as selected by a specific microinstruction field. Data may also
be entered on the bus 22 from a constant memory 128 which is preferably
implemented by any commercially available 256-word read only memory (ROM)
which holds arbitrary 16-bit constants. Data may be available as well from
the I/O devices 20, such as the display 20.sub.(1). Other data is
available from the main memory 16 and portions of instructions are entered
on the bus 22 from the instruction register 116. The main memory 16 will
be described in more detail below.
Data may be transferred from the bus 22 to the I/O controllers 18, the main
memory 16, the instruction register 116, the T register 106, or even the L
register 110 through the ALU 120. Data transfers are under the control of
microinstructions which are executed from the instruction memory 42, which
is desirably implemented by a conventional 1024 word .times. 32-bit
programmable read-only-memory (PROM).
The specific nature of the 22-bit instruction field of a 32-bit
microinstruction accessed from the instruction memory 42 will now be
described with reference to FIG. 3. As shown, the 22-bit instruction field
loaded into the instruction register 46 includes seven "sub-fields" as
follows:
______________________________________
BIT(S) SIGNAL MEANING
______________________________________
0-2 A REGISTER (R) SELECT
3,4 B REGISTER (R) SELECT
5-8 C ALU FUNCTION
9-11 D BUS DATA SOURCE
12-15 E FUNCTION 1
16-19 G FUNCTION 2
20 H LOAD L
21 I LOAD T
______________________________________
The R Select field (bits 0-4, signals A and B) specifies one of the 32
registers which comprise the register file 102 to be loaded or read under
control of the bus source field, or, in conjunction with the bus source
field (bits 9-11, signal D), one of the 256 locations to be read from the
constant memory 128. The low order two bits of the R address (but not the
constant memory address) may be taken from fields in the instruction
register 116, i.e. IR (1,2) and/or IR (3,4), as applied through a
conventional multiplexer 125 (FIG. 4). This enables the main microgrogram,
i.e. task 0, to address certain registers in the R file 102 more easily.
The ALU Function field controls the ALU 120. The ALU 120 can do a total of
48 arithmetic and logical operations. The 4-bit field is mapped by a PROM
140 into the 16 most useful functions. These functions are disclosed and
described in detail in the aforementioned parent applications Ser. Nos.
519; 153 and 733,552, both of which are hereby incorporated by reference.
The bus data source field (bits 9-11, signal D), upon being decoded by BS
decoder 52a, specifies one of eight data sources for the bus 22 as
follows:
______________________________________
OUTPUT
BS DECODER 52a
SOURCE OF DATA
______________________________________
0 Read R Register 102
1 Load R Register 102
2 Nothing (-1)
3 Kstat (assigned to disk controller
if used as one of controllers 18)
4 Kdata (assigned to disk controller
if used as one of controllers 18)
5 Memory data (from main memory 16)
6 Input device data (4 bits, remain-
der of word is 1) : MOUSE (if used
as one of controllers 18)
7 Disp (low order 8 bits of
instruction register 116, sign
extended)
______________________________________
Output 1, i.e. Load R, is not logically a source, but since the register
file (R) 102 is gated to the bus 22 during both reading and writing, it is
included in the source specifiers.
The two function fields F1 and F2 specify the address modifiers, register
load signals (other than those for the registers 102, 106 and 110) and
other special conditions required. The first eight conditions specified by
each field after being decoded by F1 decoder 52b are interpretated
identically by all tasks, but the interpretation of the second eight
decoded conditions depends on the active task. The first eight
task-independent functions are given below, whereas the latter eight
task-dependent (also referred to as "task-specific") functions will be
described later.
______________________________________
OUTPUT
F1 DECODER 52b
NAME MEANING
______________________________________
0 -- No activity
1 MAR.rarw. Load MAR 114 from ALU
120 output; start main
memory 16 reference
2 TASK Switch tasks if higher
priority wakeup pending
3 BLOCK Disable current task
wakeup until reenabled
by hardware generated
condition
4 .rarw.L lsh 1
Left shift L (one place)
5 .rarw.L rsh 1
Right shift L (one place)
6 .rarw.L lcy 8
Cycle L (8 places)
7 .rarw.CONSTANT
BUS constant ROM loca-
tion addressed by R
SELECT BUS SOURCE
______________________________________
Outputs 4-6 are modified by function fields F2=11 and F2=12, such fields to
be described in detail later.
__________________________________________________________________________
OUTPUT
F2 DECODER 52c
NAME MEANING
__________________________________________________________________________
0 -- No Acitivity
1 BUS=0 NEXT.rarw.NEXT OR(BUS=0)
2 SH 0 NEXT.rarw.NEXT OR (SHIFTER
OUTPUT 0)
3 SH=0 NEXT.rarw.NEXT OR (SHIFTER
OUTPUT=0)
4 BUS NEXT.rarw.NEXT OR BUS (06)
-BUS (15)
5 ALUCY NEXT.rarw.NEXT OR LALUCO
(THE CARRY USED IS THAT
PRODUCED BY THE ALU
FUNCTION WHICH LAST
LOADED THE L REGISTER 110.
6 STORE
7 CONSTANT SAME AS F1=7
__________________________________________________________________________
The ALU 120 is restricted by the mapping of its 4-bit field by the PROM 140
so that only 16 arithmetic and logical functions may be performed. The
output of the ALU 120 is transferred to the L and memory address registers
110 and 114. The T register 106 may also be loaded from the output of the
ALU 120 under certain conditions. The L register 110 is connected to a
shifter 144 which is capable of left and right shifts by one place, and
cycles of eight. Double-length shifts may also be formed. The output of
the shifter 144 is transferable to the register file 102. The output of
the MAR register 114 is decoded by a decode and control unit 148 and
transferred along the address bus 13 to the main memory 16, and more
particularly to a main memory store 17 of the main memory 16. Details of
the main memory 16 and its main memory store 17 will be described below.
As indicated above, microinstructions are executed one at a time in each
processing cycle. Generally speaking, with respect to the data section 12
of the CPU 10, a microinstruction consists of taking a piece of data from
a source register in the register file 102, operating upon it, and loading
the results into another register. For example, a microinstruction may
dictate that the contents of the 23rd register in the register file 102 be
transferred by way of the bus 22 to the T register 106. This
microinstruction would be in the form of having the R select field
equalling 23 and having the load T bit set. An additional operation may
take as many as three microinstructions. If it is desired to add the
contents of the 22nd register of the register file 102 with the 23rd
register and transfer the results to the 30th register, three
microinstructions are, in fact, necessary. The first microinstruction
would read the contents of the 22nd register into the T register 106; the
second microinstruction would read the contents of the 23rd register
through the ALU 120 and into the L register 110 and simultaneously would
define an addition operation in the ALU function field so that the ALU 120
would perform addition (the result stored in the L register 110 at the end
of the second microinstruction would thus be the sum of the contents of
the 22nd register and the contents of the 23rd register); the third
microinstruction would transfer the contents of the L register 110 through
the shifter 144 back into the appropriate destination in the register file
102.
The microinstruction is structured so that a parallelism of different
operations may be directed by a given instruction. This segmentation is
achieved by the definition of specific fields within the instruction as is
represented in FIG. 3. A given instruction is selected from the
instruction memory 42 and is transferred to the microinstruction register
46 where it is stored as shown in FIG. 2. In the preferred embodiment of
the invention and as indicated above, seven fields comprising an
instruction width of 22 bits dictate the processing operations to be
performed. Five bits (signals A and B) are used to select the location in
the register file 102 which are to be involved during a given instruction
period. If the register file 2 is not to be involved within a particular
processing cycle, this RSELECT (RSEL) field has a value of zero. A 4-bit
arithmetic and logic unit function field ALUF (signal C) specifies one of
16 logical operations, including addition and subtraction, which the ALU
120 can perform. A 3-bit bus source field BS (signal D) determines which
of the previously identified eight possible data sources are gated onto
the 16-bit bus 22 during the particular microinstruction period.
The Read R and Load R bus sources are typically used in almost every
microinstruction. With the value of two, the BS field specifies that
nothing is to be placed on the bus 22. The Kstat source indicates status
bits which would be stored within a disc controller, if used as one of the
I/O controllers 18. Kdata would consider 16 bits of disc data as a source,
again assuming a disc controller were being utilized in the system. Memory
data identifies data which would result from a fetch from a particular
location in the main memory store 17. The indicator device data could
possibly be represented by four external control bits. Disp would be the
lower 8 bits of of the instruction register 116, with bits 0-7 made equal
to bit 8 (sign extension). This particular bus source specification allows
for the definition of microcode which provides fast processing. As has
been already mentioned, the register file 102 is gated to the bus 22
during both the reading and the writing of the file 102. Thus, Load R
source is included in the source specifiers.
Whenever the register file 102 is selected for reading or writing, data is
necessarily placed on the bus 22. Therefore, the bus 22 contains data
whenever a write operation is performed on the files 102, even though some
other transfer in parallel may be made. Writing into the file 102, then,
uses the Load R condition in the BS field. If writing into the file 102 is
not specified with this field, then there would be no other use for this
field during that microinstruction. With this implementation, during an
instruction which writes data into the register file 102, the contents of
the bus 22 will be represented as zero at that time, even though data was
originally on the bus 22. This latter condition is implemented by the
address memory 40 (FIG. 2) whose inputs are connected to the instruction
register 116 and the bus 22 under the control of the signal ZERO BUS. The
bus 22 is zero when the ZERO BUS signal is true, which signal is generated
whenever the microinstruction specifies that the register file 102 be
loaded.
The advantages of using special function fields F1 and F2 can be
illustrated by the function of loading the memory address register (MAR)
114. This is a function that is performed moderately often in a
microprogram, conceivably every five microinstructions. This frequency of
use is not such that it would justify a special bit in the instruction,
but often enough so that it should be specified as a task-independent
function. Therefore, Load MAR is in the first set of eight function F1's,
i.e. F1=1. Similar rational is applied to the implementation of the
remaining functions within the set of functions.
The left shift (F1=4), right shift (F1=5) and cycle (F1=6) functions
control the shifter 144 which is responsive to the output of the L
register 110. Sixteen bits of data are transferred from the L register 110
to the shifter 144 in parallel and 16 bits which are inputted to the
shifter 144 can be left shifted, right shifted, or cycled by 8 with the
result of the operation being transferred to the register file 102 to be
stored. By the use of the function F1, values 4, 5, or 6, these task
independent functions may be specified.
Tasks may be switched to higher priority wake-up requests by the use of the
function 1, value 2 (F1=2). Current task wake-up may be disabled by the
use of the function 1, value 3 (F1=3). The function 1, value 7 instructs
that a literal constant be fetched from the constant memory 128. There are
| | |
