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Description  |
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The present invention relates to the art of programmable controllers and
more particularly to a programmable controller utilizing a standard
microprocessor.
The invention is particularly applicable as a programmable controller to
control a machine tool, or other mechanical system of the type generally
controlled by input information and output conditions and it will be
described with particular reference thereto; however, it should be
appreciated that the invention has much broader applications and may be
used in various types of installations wherein input and output
information or conditions are to be processed digitally in accordance with
a preselected program or in accordance with standard relay logic, logic
diagrams or Boolean equations.
INCORPORATION BY REFERENCE
Incorporated by reference herein is prior U.S. Letters Pat. No. 3,827,030
which discloses a programmable controller utilizing a random access memory
to process input and output information in accordance with standard logic
or relay terminology. Also incorporated by reference herein is prior
United States application Ser. No. 632,257, filed Nov. 17, 1975, by the
present inventor and related to a self-addressing feature for output
modules of the type contemplated by the present invention.
BACKGROUND OF INVENTION
In the last few years, a very advanced data processing device has become
commercially available. This device, known as a microprocessor, is sold by
various companies and generally includes a plurality of address terminals,
several bi-directional data terminals and internal control circuitry for
determining several types of machine cycles to be performed. These
microprocessors are produced in accordance with integrated circuit
technology of the PMOS and NMOS type. The versatility of these
microprocessors or "microprocessing chips", as they are known, is well
known in the art of controlling machine operation. A variety of attempts
has been made to utilize the standard microprocessor, as the heart of a
programmable controller which can control machines and logic systems.
However, generally the attempts to use the microprocessor for a controller
function have resulted in complex software requirements. The
microprocessor has relatively limited capabilities. Four or eight bit data
bus are generally available and only sixteen address lines. In addition,
the internal processing by the microprocessor is somewhat limited so that
a substantial number of software steps or program steps must be generated
to perform even somewhat simple logic operations. It is often difficult to
debug a system employing a microprocessor because there is a distinct
inability to stop the microprocessor at a selected position and then read
the internal condition of the internal registers and modify these
registers without complicated software. Also, the ability to interrupt the
microprocessor for jumping to a subroutine by external stimuli is limited
by the circuitry or locations available for this purpose. It is desirable
to provide a large number of interrupt call conditions, wherein the
general or executive program can be temporarily stopped and a standard
preset subroutine program processed. This is very beneficial in reading or
writing by the controller at certain isolated locations. In other words,
it is sometimes desirable to ignore several inputs until there is a change
in their state, at which time a separate subroutine can be processed.
Consequently, the subroutines are processed only when required. In order
to do this, it is necessary to provide a great number of separate and
distinct interrupt call conditions. An inexpensive simple arrangement for
expanding the number of interrupt call conditions is not now available in
the technology of microprocessors.
Since a standard microprocessor includes four or eight data terminals, it
is extremely difficult to process single bit information of the type
contemplated in prior U.S. Pat. No. 3,827,030. Such single bit information
requires extensive software for masking of data lines and for shifting
data between lines. This again makes the use of a microprocessor somewhat
complicated, especially for relatively simple logic conditions such as
AND, OR, COR, CAND, INVERT, etc. Microprocessing technology also has
limitations regarding debugging of output or input terminals. In many
instances, the terminal must actually be connected and operated before the
system may be debugged. This is a substantial disadvantage in use of a
microprocessor for any machine or system control function.
The present invention relates to a programmable controller using a
microprocessor and novel external hardwired circuitry to overcome distinct
disadvantages of prior attempts to use a standard microprocessor chip for
a machine or system control function. In the past, the use of a
microprocessor for control functions has required acceptance of the severe
limitation of the microprocessor and have, therefore, utilized extensive
and complex software for processing the desired input and output
information. Thus, a relatively large number of memory locations were
required for storing the extensive software program to employ a
microprocessor as a controlling system. The present invention has overcome
this disadvantage and has provided unique, novel external hardwired
circuitry for allowing the use of a microprocessor, with all its standard
limitations, in a programmable controller which can process eight bit data
words and single bit data without extensive complex software. Thus,
software needed to convert the microprocessor chip to a viable control
system is substantially reduced, with the resultant substantial reduction
in the cost of programming and the probability of unavoidable error.
Consequently, the present invention relates to an improved programmable
controller which employs a standard microprocessor. This is distinguished
from prior attempts which essentially programmed a microprocessor for a
control function. In those systems, all of the components were standard
shelf items that are put together in known form to produce a control
function under the auspices of a complex software program. This is the
antithesis of the present invention, wherein a standard microprocessor is
a component, which is used with additional circuitry to produce a total
programmable controller that requires a minimum of software and still
produces desired control functions necessary for controlling even complex
machinery and systems.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a programmable
controller comprising a microprocessor having output address terminals and
input/output bi-directional data terminals wherein the address terminals,
in accordance with normal practice, have a nominal high order impedance.
There is provided a plurality of output address bus lines having an
integrated circuit for connecting the bus lines to the address terminals
of the microprocessor. In accordance with this aspect of the invention,
the output bus terminals of the integrated circuit connecting means have a
low order impedance with a value less than about 1% of the high order
impedance of the microprocessor address terminals. In this manner, the
normal address lines extending throughout the controller system have a
lesser tendency to be affected by extraneous fields and electromagnetic
noise.
In accordance with another aspect of the present invention, there is
provided a programmable controller using a microprocessor having a
plurality of bi-directional data terminals and a plurality of address
terminals upon which binary coded addresses appear, data lines for
receiving a byte of data having a number of bits corresponding to the
number of data terminals, a first logic network for selecting one of said
bits of a byte on said data lines and a second logic network for applying
said selected bit to a selected one of said data terminals. In this
manner, a byte of information can be converted to a bit for internal
processing by the microprocessor. Consequently, a single bit of
information from an eight bit word or byte can be processed by a single
location in the microprocessor. Standard logic functions can be performed
without complex masking or shifting. For instance, if bit No. 5 of one
eight bit word or byte is to be ANDed with bit No. 2 of another eight bit
word, the fifth bit of the first word can be externally shifted to a
selected data terminal and then loaded into the accumulator of the
microprocessor. Thereafter, the second bit of the next word can be shifted
to the same data terminal and ANDed with the accumulated information. The
output on the selected single line is then directed to an addressed
position, either in memory or at an output terminal. This inventive aspect
provides an arrangement whereby bit information can be processed by the
microprocessor even though the microprocessor has been expanded to include
several bi-directional data terminals. The expansion of microprocessors to
include several data lines is considered an advance and is an advance when
processing large words, such as eight bit or sixteen bit words. However,
this capability is a distinct hinderance when attempting to logic function
two individual terminals of the system. By using the present invention,
this disadvantage of an expanded, larger capability microprocessor is
overcome by selecting one bi-directional data terminal as a single bit
processor. In this fashion, the internal accumulator is, in effect, a one
bit accumulator for bit processing.
In accordance with another aspect of the present invention, there is
provided a programmable controller of the type using a standard
microprocessor which includes means for providing a binary status code on
the data terminals indicative of the status of the machine cycle to be
processed by the microprocessor. In accordance with this aspect of the
invention, a logic decoder is used for producing a selected signal output
in response to the logic signals on selected address terminals and in the
binary status code on the data terminals. In other words, the status code
created at the beginning of a machine cycle is read and compared with
certain addresses to produce a signal. The created signal can be used
internally of the controller for hardwired functions. The provision of an
internal circuit which is controlled by the status code of a
microprocessor together with a selected address to produce a hardwired
external signal which can perform a variety of logic functions during the
normal operation of the programmable controller is not available on other
microprocessor or control systems.
In accordance with a further aspect of the present invention, there is
provided a programmable controller including a microprocessor and using
the binary status code on the data terminals indicative of the status of a
machine cycle to be processed by the microprocessor. In this system, there
is provided a means responsive to the binary status code for latching the
address lines to a logic true condition in the more significant bits of
the address lines. In this manner, when processing information based upon
the status code, the more significant address lines are connected to high
level locations in external memory circuits. These memory locations are
generally unused locations or little used locations and do not require
continuous writing and rewriting which may affect the actual program steps
stored in memory. The program is generally written in lower level memory
addresses. This address increasing arrangement is used to assure that
writing of random information into memory during certain functions of the
programmable controller is at the seldom used high address levels.
In accordance with another aspect of the present invention, there is
provided a manner by which the microprocessor can be shifted into the HOLD
state by a software command. This is accomplished by providing a hardwired
circuit responsive to one data line of the microprocessor and a selected
address terminal of the microprocessor. In this manner, a HOLD command can
be inserted at any software position for debugging the programmable
controller without placing the microprocessor in a HALT state which is not
desired and difficult to vacate.
In accordance with another aspect of the present invention, the
programmable controller is provided with a real time clock for producing
an output pulse for shifting the controller to a subroutine at a
preselected time interval. A logic decoding means produces a selected
signal in response to the logic at selected ones of the address terminals
and the logic in the binary status code which appears at the data
terminals. Means are provided for disabling the real time clock upon
production of this selected signal. In this manner, the real time clock
may be disabled by a software command by using the binary status code
appearing at the first of the machine cycle in a microprocessor.
In accordance with another aspect of the present invention, there is
provided a programmable controller using a microprocessor. The
microprocessor includes the standard actuatable terminal means for
shifting the microprocessor from a program being processed to a selected
subroutine program at a memory location having a binary coded address
received by the microprocessor at the data terminals. In this improved
programmable controller system, there is provided a plurality of input
devices each of which has an assigned subroutine with a given memory
address code for processing by the microprocessor when each of the input
devices is actuated, a first set of data lines connected to the data
terminals, a second set of data lines connected to the external devices,
data transfer means interconnecting the first and second sets of data
lines, means for creating an INTERRUPT signal upon actuation of one of the
input devices, interrupt means responsive to said INTERRUPT signal for
actuating the actuatable terminal means, isolation means responsive to the
INTERRUPT signal for isolating the second set of data lines from the first
set of data lines, and decoding means for identifying the actuated input
device and for producing a selected partial memory address code
corresponding thereto. This partial address code has fewer bits than a
full memory address for a stored subroutine. There is also provided
address input means for applying the selected partial memory address code
and a fixed binary code to the first set of data lines for selection of a
subroutine corresponding to the actuated input device. In accordance with
this aspect of the invention, a partial address is created during a
selected interrupt cycle. This partial address is combined with a fixed
binary address code to locate the memory address of the subroutine to be
processed for a selected interrupt condition or call. Consequently, a very
minor code can be used for determining the location of the subroutine
corresponding to various predetermined interrupt requests.
In accordance with another aspect of the present invention, there is
provided an external means for storing a number of separate and distinct
memory addresses corresponding to external interrupt request inputs. When
one of the external interrupt request inputs is actuated, the
microprocessor chip is shifted into a preselected priority interrupt
level. Thereafter, a separate and distinct memory address is applied to
the data bus for location of the subroutine to be processed for the
actuated external interrupt request. In this manner, a large number of
separate interrupts can be used without requiring complex circuits. By
using this aspect of the invention, a selected one of a small number of
interrupt levels can be used to accommodate a large number of external
interrupt requests. After actuation, a binary coded call to a given
subroutine is directed through data bus to the microprocessor. This call
includes a memory stored subroutine, without employing the normal hardware
selected restart call of a subroutine used in a standard microprocessor,
such as an Intel 8080 unit. Indeed, the restart subroutine selecting
circuit can be deactuated when the selected one of the interrupt levels is
actuated to process a large number of add-on interrupt requests. This
interrupt expansion at a selected priority level provides a simple means
for using interrupt processing instead of repetitive review of external
conditions by the executive program.
Still further aspects of the present invention will be appreciated from a
consideration of the preferred embodiment of the present invention taken
together with the description of the embodiments and the components and
advantages relating to the various features of the preferred embodiment.
The primary object of the present invention is the provision of a
programmable controller, which programmable controller can employ a
standard microprocessor without requiring the complex software generally
associated with microprocessors.
Another object of the present invention is the provision of a programmable
controller, as defined above, which controller employs external circuitry
for reducing the software requirements of the microprocessor in
controlling a machine or system.
Yet another object of the present invention is the provision of a
programmable controller, as defined above, which controller includes an
arrangement for reducing the impedance of external conductors used for
addressing various external components.
Another object of the present invention is the provision of a programmable
controller, as defined above, which controller utilizes the binary status
code of a standard microprocessor for developing hardwired signals to
process information in the controller.
Another object of the present invention is the provision of a programmable
controller, as described above, which controller can shift from a byte
mode of operation to a bit mode of operation for individual processing
steps.
Still a further object of the present invention is the provision of a
programmable controller as defined above, which controller provides an
arrangement for software addressing of specific signals, such as a real
time clock inhibit instruction.
Still a further object of the present invention is the provision of a
programmable controller, as defined above, which programmable controller
includes an arrangement for substantial expansion of the interrupt
capabilities generally associated with the microprocessor.
BRIEF DESCRIPTION OF DRAWINGS
The above objects and advantages will become apparent from the following
description taken together with the accompanying drawings in which:
FIG. 1 is a schematic view setting forth a preferred embodiment of the
invention and various modules employed therein;
FIG. 2 is a status chart indicating the data line status coding at the
status conditions of each machine cycle;
FIGS. 2A, 2B and 2C are address coding used for two input/output addresses
and a memory address, respectively;
FIG. 3 is a pulse chart for timing functions of the standard 8080 Intel
microprocessor as adapted for use in the preferred embodiment of the
invention;
FIG. 4 is a composite view made up of separate and distinct sections
labeled FIGS. 4A, 4B, 4C, which sections are to be taken together and are
jointly referred to in the specification as FIG. 4, and illustrating the
central processing module of the preferred embodiment of the present
invention and employing a major portion of the inventive features of the
present invention;
FIG. 5 is a schematic logic diagram illustrating the HOLD REQUEST function
of the preferred embodiment, together with an abbreviated subroutine which
may be employed therewith;
FIG. 6 is a schematic logic diagram illustrating an expansion module for
expanding the interrupt capability of the programmable controller;
FIG. 6A is a schematic wiring diagram illustrating certain primary features
of the diagram illustrated in FIG. 6 and combining certain related subject
matter employed in the central processing module illustrated in FIG. 4;
FIG. 7 is a schematic wiring diagram illustrating a PROM module employed in
the preferred embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating a RAM module of the type
contemplated for use in the preferred embodiment of the present invention;
FIG. 9 is a logic diagram showing the features employed in a byte module
and certain circuitry used for converting a byte module to a bit output
unit;
FIG. 10 is a schematic logic diagram showing a bit input/output module
driver for addressing several external input and/or output terminals;
FIG. 11 is a single input/output module of the type addressed by the module
shown in FIG. 10 and as contemplated in the preferred embodiment of the
present invention;
FIG. 11A is a schematic diagram showing the transceiver function employed
in the preferred embodiment of the present invention and in the circuit
shown in FIG. 11;
FIG. 12 is a schematic view in representative program of a simple logic
function which is to be programmed in a byte mode;
FIG. 13 is a simplified program to perform the function of the program
shown in FIG. 12 but when the bit mode of operation is employed in the
preferred embodiment of the present invention;
FIG. 14 is a schematic illustration of the circuitry employed in FIG. 4 for
converting to a bit mode of operation on input to the microprocessor with
certain modifications for purposes of explanation;
FIG. 15 is a schematic view illustrating conversion of an output circuit to
accept a single bit of information and similar to the bit circuit
illustrated in FIG. 9;
FIG. 16 illustrates a module for creating an interrupt condition to read
external switch conditions to avoid continuous processing of these
switches during the normal operation of programmable controllers;
FIG. 17 is a simplified view showing one feature from FIG. 4 used in the
INTERRUPT processing mode;
FIG. 17A is a chart indicating the restart code appearing on the data lines
after interrupt conditions have been acknowledged by the microprocessor;
FIG. 18 is a simplified view showing one gate employed during the INTERRUPT
feature of the circuitry shown in FIG. 4;
FIG. 19 is a simple program employed in one of the INTERRUPT states of the
microprocessor shown in FIG. 4; and,
FIG. 20 is a combined logic view and output graph for the device employed
in the preferred embodiment of the invention to create hardwired signals
in response to the binary status code appearing at the initial portion of
the machine cycle in the microprocessor employed in the programmable
controller. de
GENERAL SYSTEM
Referring now to the drawings wherein the showings are for the purpose of
illustrating the preferred embodiment of the invention and not for the
purpose of limiting same, FIG. 1 shows a programmable controller A for
controlling machines, processes and other systems in response to input
information from inputs and existing conditions or other parameters. The
inputs, conditions and parameters are directed to the controller A from
various external terminals and locations which are capable of providing
binary information as single bit or multiple bits, i.e. bytes. These
external terminals may be switches, decoded thumbwheels, lights, decoded
analog data and binary coded conditions. In accordance with normal
practice the controller includes memory locations and is processed in
accordance with a program stored as a plurality of steps or instructions
in such system memory. Certain random access memories are provided for
storing intermediate information or data. This memory can also be used for
some program storage although a program read only memory is generally used
for storage of the program information or steps.
As illustrated in FIG. 1, programmable controller A is a digital processing
system including a plurality of separate and distinct plug-in modules
interconnected by a plurality of control lines, which are generally in a
motherboard connecting system, except for remote input/output modules. The
basic modules and control lines therefor are schematically illustrated in
FIG. 1 wherein a central processing unit module (CPU) 10 or module CP711
employs a standard microprocessor as its central control unit. The central
processing unit is shown in FIG. 4. This microprocessor is a known MOS
integrated circuit chip which includes internal registers, counters,
pointers and associated logic circuitry well known in the art. The
microprocessor, which is shown in more detail in FIG. 4, has a number of
output address terminals, a number of bi-directional data terminals, means
for setting the chip into various known states and means for providing a
status code on the data lines at the start of each separate command.
Although a variety of microprocessors having these standard capabilities
could be used, the preferred embodiment of the present invention involves
the use of an Intel 8080 microprocessor which has sixteen address
terminals and eight bi-directional data terminals. The controller A
incorporates the various inventions relating to the use of a
microprocessor for processing input and output information to control a
preprogrammed series of events of a machine, process, etc. The input
information in the preferred embodiment of the present invention is
digital information both at the input and output; however, converters for
conversion between analog and digital could be used to interface between
the system shown in FIG. 1 and various analog inputs and/or outputs. The
CPU module 10 is communicated with the other modules to process input and
output information on lines D.sub.0 -D.sub.7. A brief description of the
separate modules will be sufficient to illustrate their intended use with
the CPU module 10 and the overall operation of programmable controller A.
To initially program and debug the controller A, there is provided a direct
access module 20 which takes over control of several control lines
connected to CPU module 10. Thus, it is possible to directly program the
memories in controller or system A by an external device, such as a
schematically represented digital computer 22. In the illustrated
embodiment, the computer is connected to direct access module 20 by
schematically represented lines 24. When a HOLD REQUEST signal is directed
from module 20 to CPU module 10, computer 22, or other external control
devices, obtains control over the address lines, the input designation
line DBINP, the READ/WRITE line, and the D.sub.0 -D.sub.7 data lines, and
other lines shown by the arrows in FIG. 1. When this happens, the CPU
module is essentially disconnected from the rest of the controller and
computer 22 can load memories, i.e. to program the controller, and
actually operate the controller, as in debugging and troubleshooting. The
direct access module is used to load all memories of system A with the
desired logic, set inputs and outputs to the desired conditions,
selectively read the contents of the memory or the various input and
output circuits, reset controller A, provide intermediate stop and run
operations for the controller A, and check the status of all the memory
positions and registers of controller A including the registers of the
microprocessor MP in CPU module 10. The direct access module is used for
flow of data to and from system A under the control of an external unit
such as a computer, external tape reading devices, teletype, etc.
In order to accomplish transfer of control to module 20, microprocessor MP
of module 10 is placed into the HOLD state, which will be explained later.
The external programmer, such as a computer or tape reader, sends data to
and from controller A through data lines D.sub.0 -D.sub.7 and the location
of the data is controlled by address lines A.sub.0 -A.sub.15. By placing
the microprocessor of module 10 in the HOLD condition or state, instead of
the HALT state, the functions of the microprocessor can be taken over by a
programmed signal or request from module 20 in a manner to be explained in
connection with FIG. 5. Also, control by the microprocessor can be
reestablished by a simple command without complex programming required
when the microprocessor shifts to a HALT state. It is not necessary to
provide an initiation pulse for again obtaining control over system A by
module 10. As soon as the HOLD condition is released, the CPU module 10
again assumes control over the lines illustrated in FIG. 1. This provides
a convenient manner for giving direct access to the controller A for
programming and debugging and then for releasing the controller for
control, which is isolated from module 20.
As will be explained later, CPU module 10 may be interrupted by external
conditions to interrupt the program and shift control over the
microprocessor to a memory stored subroutine. This is a standard INTERRUPT
feature of most eight bit microprocessors; however, in accordance with one
aspect of the invention, controller A includes a plurality of separate
interrupt expansion modules, three of which are schematically illustrated
as interrupt expansion modules I, II, III, or 30, 32 and 34, respectively.
Module 32 is schematically illustrated in more detail in FIG. 6, which
showing is representative of an interrupt expansion module connected to
and controlled through the first interrupt expansion module 30. The
difference between the first expansion module and subsequent expansion
modules is that the enabled terminal E of module 30 is tied to a logic 1,
which in practice is five volts throughout controller or system A. The
subsequent modules 32, 34, and any additional modules, include an input
enable logic at terminal E which is controlled by the condition of
preceding interrupt expansion modules. This connection arrangement
provides a priority level system wherein the interrupt inputs of module 30
have a priority over the interrupt inputs of subsequent interconnected
expansion modules 32, 34, etc. In each of the interrupt expansion modules,
in the illustrated embodiment, there are provided sixteen separate
interrupt inputs which are schematically illustrated as a plurality of
single pole, grounded switches 30a-30x, 32a-32x and 34a-34x. These
interrupt inputs can be logic inputs which contain information requesting
a shift of module 10 into the interrupt state for processing of a selected
subroutine. Thus, actuation of an input will cause the microprocessor MP
of module 10 to interrupt and shift into the subroutine which is to be
processed. Then control is returned to the executive program of controller
or system A. By using this interrupt expansion arrangement, a great number
of selectable subroutines can be provided and called by providing an
interrupt request at one of the several schematically represented logic
inputs. The executive program of system A requires the processing of a
"look" command or sequence for those data or logic inputs and outputs
under interrupt control only when an interrupt request is received
indicating that a certain terminal or terminals should be scanned and/or
updated.
When an interrupt request is received by the CPU module from a terminal of
an expansion module, the microprocessor shifts to an interrupt state and
data from the expansion module selects or "calls" a given subroutine by an
address on lines D.sub.0 -D.sub.7. Then the calling input or outputs will
be processed according to the desired and requested interrupt subroutine.
Thereafter the subroutine will shift command back to the main program. As
will become more apparent when discussing in detail the interrupt features
of the present invention, the various interrupt requests will have a
certain, preselected priority order which will determine whether or not a
called subroutine is interrupted by a subsequently called subroutine. If
there is no interrupt request, then the executive program is processed
repeatedly without processing the interrupt subroutines. Consequently, the
subroutines are called and processed only when needed. The number of
expansion terminals of modules 30-34 can be increased to larger values.
The only practical limitations are the memory capacity which can be
expanded to various capacities and the time available for processing
interrupt subroutines.
By providing the interrupt expansion modules, the microprocessor of system
or controller A can be interrupted a substantially greater number of times
than is available on known microprocessors. Thus, the normal
microprocessor interrupt concept of priority evaluation and jumping to a
subroutine called by a particular interrupt can be used for many separate
inputs or conditions. This saves programming time and allows the use of
subroutines which may be stored into the memories of system A for only
periodic use. The versatility of system A is thereby greatly expanded
while still using a readily available, relatively inexpensive
microprocessor.
Module 40 which will be discussed in more detail with respect to FIG. 7 is
a programmable read only memory (PROM) module. The PROM module is used in
system A for the purpose of retaining permanent logic at various addressed
locations determined by the logic on lines A.sub.0 -A.sub.15. In practice,
the executive program and the various subroutines are generally,
permanently stored at various addressed locations within PROM module 40.
This memory module is used for long term or permanent storage of the
program and employs MOS memory chips that are erasable upon exposure to
ultra violet light and are programmable by means, such as computer 22 or a
tape reading device through direct access module 20. In practice, the PROM
module has a capacity of 4,096 eight bit words. The number of words
available in the read only memory module 40 may vary according to the
desired capacity of system A. In practice, the memory technology used in
module 40 is static silicon gate MOS erasable and electrically
reprogrammable read only memory chips.
During normal operation of controller A, data is directed from module 40 on
lines D.sub.0 -D.sub.7. The parallel transmission of binary data on these
lines provides an eight bit word which is addressed by the logic on lines
A.sub.0 -A.sub.15. In FIG. 1, it is indicated that the data lines D.sub.0
-D.sub.7 are bi-directional at PROM module 40. This is only for the
purpose of loading the memory during the programming and debugging
operation through direct access module 20. The memory chips of module 40,
in practice, are not erasable under normal circumstances; therefore,
continuous application of power to this particular module is not required
for the purpose of retaining the stored logic. Of course, a variety of
different types of read only memories could be used for storing the
program information for system A without departing from the intended
spirit and scope of the invention as schematically illustrated in FIG. 1.
Referring now more particularly to the random access memory (RAM) module
50, this memory module can be updated periodically during use of system or
controller A. Various random access memory modules could be used in system
A; however, the basic features of the ROM contemplated in the illustrated
embodiment of the invention is shown somewhat in detail in FIG. 8 and will
be described later. The random access memory module 50 includes a somewhat
standard parity checking circuit 52 schematically illustrated in FIG. 1.
In this manner, information to and from the random access memory chips
will be checked for parity in accordance with standard practice to
determine an error. In practice, module 50 employs random access solid
state memory chips with a capacity of 4,096 eight bit words. In this
module, an external battery supply is used for retaining the information
or data at the several locations on module 50, until the information or
data is changed intentionally by operation of controller A in a manner to
be described later. The semiconductor memory technology used in module 50
is static N-MOS random access technology. The module 50 is addressable for
both reading and writing by the logic on lines A.sub.0 -A.sub.15, which
address selects the desired address of the RAM module and directs the
eight bit word from that location in parallel onto data lines D.sub.0
-D.sub.7. The DBINP logic and the R/W logic determines whether or not the
data is being inserted or read from module 50. Operation of a random
access memory in conjunction with a microprocessor or other type of
digital programmable controller is known and various systems could be
employed.
In addition to the PROM module 40 and the RAM module 50, it is possible to
provide additional memory which may be in the form of PROM and/or RAM. The
parity circuit 52, in practice, is of the type which provides a nine bit
word and circuitry necessary to generate and check one bit of odd parity
for each word. When an eight bit word is written into the memory, parity
generator tests the word and generates a ninth bit which will be either a
logic 1 or a logic 0 such that the resulting nine bit word will always
contain an odd number of logic 1 conditions. When a word is read from the
memory, parity check circuitry checks to be certain that the word still
contains an odd number of logic 1 signals. If the check circuit encounters
an even number of logic 1 signals, the processor is interrupted in
accordance with standard microprocessor practice. Other parity checking
circuits or systems could be employed so that errors in the accessed
information can be detected.
Programmable controller A employs a standard microprocessor which has eight
data terminals and sixteen address terminals. In this manner, an eight bit
word or byte can be serviced simultaneously by the microprocessor. This
capacity provides distinct advantages with respect to a reading of several
inputs and writing into several outputs. However, the logic processing of
a single bit in an eight bit word such as ANDing, ORing, or INVERTing,
presents substantial difficulty. A substantial amount of software
programming is required to logic process a single bit of an eight bit word
or byte. This requires memory space and extensive programming. This
disadvantage is even more serious in controlling machines and process
because a great number of simple logic functions are required. In
duplicating a standard relay logic diagram or ladder diagram much of the
processing is logic processing of single bit information. Thus, to process
this single bit information with an eight bit data capacity drastically
increases program storage space and control complexity. For instance, when
a single input is to be compared with a single output, the use of eight
bit input information is a disadvantage. When memory addresses or binary
coded data is being transferred or processed, then the large number of
data lines is beneficial. To overcome logic processing disadvantages
caused by increasing the capacity of the microprocessor, the present
invention provides circuitry for obtaining one bit information which can
be logic processed on a preselected data line, such as line D.sub.0, in a
manner similar to a single bit data processor. Thus, it is a relatively
simple process to AND, OR and INVERT logic at various inputs and outputs
to provide logic functions which are rendered more complex with the advent
of the expanded eight bit microprocessor. To illustrate the use of both
the byte and bit modes of operation, there is illustrated a byte input and
output module 60 and a bit input and output module 70. Module 60 has a
series of input words each of which has eight data bits. These words are
created by various inputs, such as thumbwheel network 62, which is
illustrated in FIG. 9 as thumbwheel units 62a, 62b. In a like manner, the
output words from module 60 are illustrated as display signals in a
display unit 64, which in FIG. 9 is illustrated as two output or display
units 64a, 64b. Thus, module 60 is used to input and output a byte of
information as an eight bit word into various | | |
