A distributed function processing system utilizing a conventional microprocessor operated as a text processor in combination with a plurality of other autonomous processing devices arranged to operate in a coherent processing system. One of the autonomous processors which is a memory control processor serves to periodically overlay a random access accelerator memory with the contents of a main memory system and concurrently resolves conflicts among various other autonomous memory service requests. This processor, therefore, accommodates the data rates of the main memory. The other processor is a display processor which generates signals to a video display system to provide a visual interface to the user and is therefore tied to the video rate. Accordingly, the processing burden is distributed within processors entailing differing rates operating autonomously. The memory control processor resolves and accommodates all of the memory service requests in the system and also performs control operations to support high speed I/O devices. Logic is provided to handle the other interrupts. Also, there is page mapping for context switching of a reference page and repeating logic for decoupling this processor from the other processors. This arrangement allows convenient expansion into plural work stations each sharing a common memory.
A word processing system with provision for operating a fixed disk via a fixed disk controller. The fixed disk controller is connected to a system floppy disk controller so that the system may be configured with up to four fixed disk drives in addition to or in lieu of floppy disk drives. The system has a display for exhibiting alphanumeric information, a first controller connected to the display for controlling the exhibition of the alphanumeric information, a second controller connected to the first controller for controlling the transfer of data to and from a data storage device, and a fixed disk controller connected to the second controller for controlling the transfer of data to and from a fixed disk. According to another embodiment of the invention, the floppy disk controller includes a DMA controller and a memory for use with both floppy disks and fixed disks.
A digital data processor comprises a high speed processor (50) having input ports (52) and output ports (54), a memory (56), and a slow speed support processor (58), the memory being accessible to both the high speed and slow speed processors. The high speed processor can effect processing in dependence upon parameters written into the memory by the slow speed processor and which may have been derived by analyzing data supplied to the slow speed processor from the high speed processor via the memory.
A multi-source/receiver data processing system has a communication bus of at least one transfer medium. Clock signal generators have different clock frequencies with respect to each other. To prevent sources and/or receivers having a slow clock signal generator from being excluded as rightful participants from an action concerning a communication, the system determines whether said bus is "ready" for executing an action using first and second detecting means whereby it can allocate a first and a second period of time thereto, respectively. When a source/receiver determines that this second period of time has expired, the bus is indeed ready for this source/receiver and all further source/receivers which have meanwhile determined during their first period of time that the bus in ready, so the bus can be occupied by this action.
A distributed computer system comprising a plurality of engines where each engine is useable to form a separate, integrated computer system. The distributed computer system is the functional equivalent of the separate, integrated computer system. An engine on a computer chip has mappable I/O pins that provide selective and mappable access to internal chip locations. A mapper is provided on the chip for mapping the I/O pins. One or more chips with mappable pins are employed to form a computer engine.
A distributed computer system comprising a plurality of engines where each engine is useable to form a separate, integrated computer system. The distributed computer system is the functional equivalent of the separate, integrated computer system. An engine on a computer chip has mappable I/O pins that provide selective and mappable access to internal chip locations. A mapper is provided on the chip for mapping the I/O pins. One or more chips with mappable pins are employed to form a computer engine.
