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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data processing systems, and more
particularly to a processing system comprising a plurality of heterogenous
processors arranged to operate as a word processor.
2. Description of the Prior Art
In the recent past the advent of LSI circuitry has enabled wide use of low
cost data processing devices commonly referred to as microprocessors. Most
such microprocessors comprise a central processing unit, or a CPU, which
in association with a primary memory, communicates with the outside world
by way of input and output ports. While there has been improvement in the
integration of the CPU and particularly in the switching time thereof, it
is the integration of large scale memory chips that is the main element
rendering such microprocessors possible. Typically, in the interest of
fast access time, such memory elements take the form of a random access
memory (RAM) and are thus directly addressable with an access time in the
instruction time domain of the CPU. Thus, the memory access function
became inherently compatible with CPU sequences and many control schemes
previously performed by switching logic were converted to stored program
form to be thus implemented in a microprocessor.
Semiconductor memory although now integrated extensively, is still
relatively expensive for large data storage applications. Accordingly,
most prior art systems utilize a secondary storage, usually much slower,
for the on-line storage system. The primary storage then functions as an
accelerator memory for active on-line data in order to better match the
memory access rate with the CPU instruction rate.
In the past, there have been many techniques developed to accommodate this
memory expansion function. Most such techniques, however, entail the use
of the CPU as the servicing module through which the memory expansion is
performed. Thus, during the execution of a particular instruction sequence
involved in some logical process, interruptions would be periodically
required for memory service. Adaptation of a microprocessor serving as a
CPU to perform logical operations then becomes increasingly difficult as
more use of secondary storage is required. Use of secondary storage
becomes even more pronounced when microprocessors of this kind are
combined to function in word processing systems.
Word processing, as now used in the art, is a term denoting automation of
many services previously performed by a secretary. These functions when
automated, however, require normally large main memory systems where
functions like form letter preparation or standard paragraph insertion are
exemplary in the volume of data storage that they require. Due to
considerations of cost, data of this bulk is still best handled by serial
secondary storage devices like Charge Coupled Devices (CCD), bubble
memory, discs or magnetic tape.
One other feature particular to microprocessors is the handling of the
input-output interfaces. In addition to memory expansion, microprocessors
normally include as a central processing task the maintenance of the input
and output ports. Since the CPU is a sequential device, the periods during
which it maintains the interface are frequently referred to as interrupt
periods during which no other operation can again occur. Thus, the
undivided attention of the CPU alternates either to the problem operations
or the servicing of input, output and memory. One typical output servicing
function is for the display interface which normally requires a large
servicing sequence. Typically the display is made by devices like a CRT
which because of its physical constraints requires updating maintenance
and which often require memory service to accommodate the amount of test
normally displayed.
The above functions each relate to physical time constraints which
encompass a very wide bandpass. On the low end the asynchronous real time
inputs from the operator (e.g., keyboard stroke) entail program sequences
which are not critical in their execution time. At the high end, the video
display dictates very high data refresh rates fixed to the vertical and
horizontal sync system of a CRT.
Heretofore most prior art systems attempted to accommodate these diverse
requirements in a singular system which therefore entailed complex
architecture and became quickly frozen in the amount of expansion or
modification that can be achieved. Thus most such prior art systems either
traded features for complexity or reduced the function complement of the
system.
Word processing systems are best accommodated in work station clusters
which may share a common memory. Where the memory is tied to a complex
system structure expansion into additional work stations becomes
increasingly difficult. For all of these reasons the system described
herein is conformed in autonomous processing segments which therefore
allow for convenient expansion of both the operating functions and the
number of work stations forming a cluster.
SUMMARY OF THE INVENTION
It is therefore the purpose and object of the present invention to combine
a plurality of heterogenous processors into one system serviced by a
single main storage system.
Further objects of the invention are to provide a data processing system
utilizing a plurality of processors where the failure of one processor
only reduces system performance rather than producing a complete system
shutdown.
Yet further objects of the invention are to provide a word processing
system which integrates, on a logical priority basis, many processing
requirements into one.
Briefly these and other objects are accomplished within the present
invention by combining a microprocessor, such as the microprocessor made
by the National Semiconductor Corporation, 2900 Semiconductor Drive, Santa
Clara, Calif. 95051, under the Model Number IMP-16C, with two special
purpose processors; one for the maintenance of a CRT display, and the
other for the expansion of virtual memory and accommodation of direct
memory access requests. For the purposes herein, the 16C microprocessor
operates as the main processor and only as a result of its software are
the other processors involved. The use of a commerical device at this
critical junction is particularly advantageous because of the inherent
reliability of mass produced items, cost advantages, and the standardized
microcode utilized therein.
For purposes of clarity, the 16C microprocessor will be referred to herein
as the test processor since this is the primary function embedded therein.
Similarly the processing segments directed at maintaining and processing
data for display will be referred to as the display processor. Lastly, the
expansion of memory or the virtual memory operations together with block
transfer I/O operations are carried out by a processor referred to as the
memory control processor. The text, display, and the memory control
processor are all connected to a main system bus; the text processor
including an interface control unit for matching the commercial processor
with the specially developed other parts of the system. In addition to
these connections, the system bus also interfaces with various peripherals
such as a head-per-track disc memory referred to herein as the micro-RAD,
a set of replaceable or floppy discs, the input devices or keyboard, the
hard copy output device or printer and a communication interface for
common carrier or high speed local communication. Although reference is
made above to a head-per-track disc main memory, other serial memories
like the aforementioned CCD, bubble or any similar lower cost store is
equally compatible with the system implemented herein. Thus a disc memory
for storing the bulk or full repertoire of data and instructions necessary
for a problem solution is exemplary only, all other stores being subsumed
thereunder.
In more detail the system bus, which serves as the primary communication
path between all of the processors involved in the system consists of an
address bus, a data bus and a plurality of control lines. In addition to
these lines above, there is a system clock line which serves as the basic
system clock organizing the overall system. All bus data transfers are
therefore synchronous with the system clock and the clock aperture sets
the time interval within which the various bus leads must assume their
proper binary value.
The address bus is 17 bits wide and the data bus is 16 bits wide, all leads
thereof being assigned to carry the particular data word associated with
the address. The remaining leads previously identified as the control
lines in addition to the normal housekeeping functions, include 16 task
request and acknowledge lines, the functions thereof being explained in
more detail below.
This bus arrangement is capable of two distinct modes of opertion. In the
first mode the text processor maintains all interrupt requests and
services the various peripherals. The other mode of operation entails the
use of the 16 task lines in conjunction with the memory control processor
described in a copending patent application Ser. No. 769,611 entitled
Memory Control Processor. As described in the copending system, various
devices are combined, according to operations or tasks which are either
more or less significant to the system. For example, any system fault
diagnostics should be performed as closely as possible to the occurrence
of the fault. On the other hand, tasks like idle or memory refresh are not
critical in their timing and, therefore, can be performed at any
convenient breakpoint in system operations. Between these two limits, the
remaining tasks are distributed. Again, the distribution of these
remaining tasks depends on the particular task timing and for example data
transfer from a peripheral memory device which normally entails relatively
slow transfer rates will have a lower priority than the memory write or
the memory read tasks for the Text Processor.
The task priority table is couched in hard wired logic of a configuration
analogous to that disclosed in U.S. patent application Ser. No. 769,254,
filed Feb. 16, 1977 and entitled `Task Handling In A Data Processing
Apparatus`, which is a continuation of U.S. patent application Ser. No.
518,679 assigned to the same assignee. This priority logic is contained in
the front part of the memory control processor and the memory control
processor therefore has absolute control over the bus system. In
distinction over the prior application the presently disclosed task logic
includes feedback elements by which the presently serviced task is latched
out of the priority comparison. Thus during convenient breakpoints in a
higher priority task lower priority requests will be serviced until they
achieve breakpoint status.
Each task within the above logic entails a servicing sequence, similar to
an interrupt operation of a microprocessor. The sequences each include
breakpoints returning back to the task priority logic the control to
service any other tasks occurring in the meantime. This breakpoint
arrangement resolves previously irreconcilable conflicts, thus
accommodating the various devices in the system which have different
rates. Thus, the prior modes of interrupt processing has been modified in
favor of a task switching sequence wherein each task being serviced is
temporarily removed from priority consideration to make room for the next
requesting priority.
The test processor itself is conventional in its mode of operation and
therefore includes the conventional interrupt logic provided by the
manufacturer. Without the use of the task logic in the memory control
processor, the text processor can still service many of the interrupt
requests from the peripherals in a conventional manner. Such, however,
reduces the processing speed and efficiency of the system. In addition,
the text processor includes a zero page mapping arrangement for context
switching by which a particular page of memory is brought in according to
the operating mode selected.
Functionally the text processor is assigned the low speed asynchronous
input processing, as for example that originating at a keyboard. The cost
of memory however is high resulting in a relatively small working store
and therefore any bulk data operations necessarily entail data transfers
between the lower speed main memory and the text processor itself. To
provide for less costly working store, the memory control processor
includes a random address page buffer store which the text processor can
directly address. The page buffer store acts as the accelerating memory
into which a large virtual memory is overlayed on demand. For that reason
the memory control processor includes elements for carrying out the
necessary memory overlays described in detail in said aforementioned
application Ser. No. 769,611 filed on the same date herewith. Most of the
external bus use in a system of this kind, and particularly in a system
dedicated to operations like editing or text processing via a full-page
display, is in the form of large memory transfers and a separate memory
control processor is therefore assigned to organize the bus use. These
functions are combined to form one integral system comprising autonomous
modular subsystems each dedicated to a particular function. This modular
approach, by function, greatly simplifies, the complexity of each module,
allowing for convenient expansion of selected modules as need arises and
reducing any checkout complexity.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a general block diagram of a data processing system constructed
to cooperate on the basis of the inventive features herein;
FIG. 2 is a block diagram of a task priority logic system constructed
according to the present invention;
FIG. 3 is a block diagram of a memory control processor useful with the
operation of the inventive features herein;
FIG. 4 is a generalized arrangement of a display processor adapted for
cooperative use with the inventive features disclosed herein;
FIG. 5 is a logic diagram of an inventive interface system constructed
according to the present invention;
FIG. 6 is a timing diagram of the external bus system utilized herein;
FIG. 7 is yet another timing diagram of the external bus system utilized
herein;
FIG. 8 is a logic diagram of a repeater stage constructed according to the
present invention for combining a commercial processor with the system
disclosed herein;
FIG. 9 is a timing diagram of a set of selected signals entitled in the
operation of the repeating logic shown in FIG. 9; and
FIG. 10 is a generalized diagram of a commercial processor useful herein.
DESCRIPTION OF THE SPECIFIC EMBODIMENT
While the foregoing illustration is set forth in the environment of word
processing, such is for purposes of description only. It is to be noted
that display word processing typifies one of the more difficult data
processing operations, and the implementation of a data processing system
adapted for such use will, therefore, accommodate many if not most other
processing problems. It is therefore contemplated to present by way of
this example one embodiment of a data processing system configured for one
particular use, the analogical expansion thereof to uses other than those
described being obvious to those skilled in the art. Accordingly, no
intent to limit the scope of the invention by way of the choice of use
selected is expressed.
Similarly, the implementation of the various subsystems disclosed includes
integrated chip elements at various levels of integration. As will be
obvious to those skilled in the art, other levels of integration are
possible and the implementation selected is once more to be considered as
exemplary only and not limiting.
SYSTEM DESCRIPTION
As shown in FIG. 1, a word processing system generally designated by the
numeral 10 comprises a bus system including an address bus A, a data bus D
and a system bus S. Buses A and B are conventional in their structure,
including the necessary clock signals to organize system operations. Bus
S, on the other hand, is a loosely organized set of signal leads connected
to integrate the distributed functions of the present system and is
identified as a bus for purposes of nomenclature only. Connected to the A
and D buses are the various processing elements of the system. More
specifically, a processor identified herein as a text processor 50 is tied
across an interface stage 51 to buses A and D. Text processor 50 may be
any conventional microprocessor and for the purposes herein the above
identified microprocessor IMP 16C, made by National Semiconductor, can be
utilized.
Also connected to buses A and D is a display processor 100 which, in turn,
drives a cathode ray tube 101. Connected further to buses A and D is a
memory control processor 150 which, by means to be further described,
provides both the control over all bus traffic and expansion of virtual
memory for the processing elements of the system.
Buses A and D are also tied to various other peripheral and input and
output devices. Specifically, tied both to buses A and D is a
communication interface 11 through which the present processing system can
communicate with various other systems. Also connected to buses A and D is
a keyboard 12 with its associated interface 13, a high speed printer 14,
with its interface and control 15, an auxiliary magnetic storage system 16
with its associated control stage 17, a plurality of replaceable or floppy
disc flies 18.sub.1 - 18.sub.3 with their associated control 19 and a
serial memory disc 20 (or other serial store) with its associated control
21.
This configuration of the system allows for a bimodal manner of operation
where, for example, the text processor 50 may, in its conventional manner,
directly service the interrupt sequences for either the keyboard 12, the
printer 14, or the display processor 100. In a similar manner, i.e., by
way of the interrupt sequence available in this commercial processor, the
various memory devices can be brought in. In this mode, however, the
relatively slow addressing speed of the various memory devices, i.e., disc
16, and floppy discs 18.sub.1 -18.sub.3 slow down significantly the
operation of the text processor. Once addressed, the data rates from such
memory devices are high, often higher than the cycle rate of the text
processor. Similarly the main memory exemplified herein as a
head-per-track disc or micro-RAD 20, while possibly at a speed higher than
the text processor, often requires servicing processes not easily achieved
in the text processor. The IMP 16C processor used as the text processor 50
includes volatile elements, which when tied to slow access memory devices,
may die out before all of the data is captured and transferred. For this
reason and to decouple the text processor from the other process rates the
interface stage 51 includes repeating logic, to be described in more
detail below, which is useful in the indirect mode of data transfer by
maintaining, on a repeat basis, the memory requests of the text processor
until any necessary memory overlays are completed in the memory control
processor 150.
Thus the function of the system is to capture data as it appears, transform
that data when necessary and to generate a response. The response, for
example, may be in terms of a video display which, because of the fidelity
and flicker rate, entails frequency levels as high as 60 MHZ. These rates
are substantially higher than the cycle rate of the text processor.
Similarly the data rates from the main memory may be higher than the
corresponding cycle rate of the text processor. In each instance, separate
processors are provided, the memory control processor 150 being described
in said aforementioned Ser. No. 769,611 and the display processor being
described in U.S. patent application, Ser. No. 769,596, filed on the same
date herewith and entitled, "Display Processor." It is these processors
that decouple the asynchronous, operator initiated, inputs handled by the
text processor from the hardware fixed time constraints.
It is for this purpose that the system includes the S bus which, in turn,
is tied to a task switching logic section 200 which is structured as an
improvement to the architecture described in the aforementioned
application Ser. No. 769,254 and which is located at the front of the
memory control processor 150.
The S bus, similar to buses A and D, is tied by signal double strand leads
S.sub.1 - S.sub.16 to the various peripherals, each peripheral providing a
particular service request designated by the subscript R to the logic
section 200 and receiving a corresponding acknowledge signal designated by
the subscript A on the same lead when the task is completed. It is
therefore to be understood that leads S.sub.1 - S.sub.16 are dual strand
leads for the purposes herein, having a separate request and acknowledge
path.
Task Switching Logic
While the general functions of logic 200 are similar to that described in
the referenced application, and furthermore are described in said
aforementioned application Ser. No. 769,611, the present system entails
operations involving task switching and a summary discussion of this task
switching logic is therefore taken up herein.
As shown in FIG. 2, the task control logic section 200, in general
breakdown, comprises an encoder stage 291 which at a plurality of input
NAND gates 290.sub.1 - 290.sub.16 receives a set of signal leads S.sub.1R
- S.sub.16R from bus S, each identifying a particular task request, and
converts such to a priority code which is applied to a register stage 292.
Register stage 292 provides the current task address (CTA) which is
applied to a program counting memory stage (RAM) 293 and to a delay
register stage 294. Register 294 produces an output CTD (Current Task
Delayed) which is decoded by a decoder stage 295. The outputs of decoder
295 are then returned in the form of signals S.sub.1.sbsb. A -
S.sub.16.sbsb. A to the gates 290.sub.1 - 290.sub.16 at the input of stage
291. By way of this feedback arrangement the currently serviced task is
inhibited from the next priority consideration. Thus the first breakpoint
occurring in the serviced task will defer to the next higher priority then
requesting. The signals CTA from register 292 select the address in the
RAM 293 into which the sequence of instruction addresses are loaded. These
instruction addresses select a particular field in a ROM 298. ROM 298
outputs into a register 299 the sequential code of the servicing sequences
in 48 bit wide code words, thus operating as the microprogram store.
During the execution of any one servicing sequence part of the register 299
output is returned to RAM 293 which, in combination with a branch stage
297, allows the programmer flexibility over the servicing microprograms.
Furthermore, signals S.sub.1.sbsb. A - S.sub.16.sbsb. A, code combination
MF from register 299 and a signal CV to be described, control the branch
stage 297. RAM 293 therefore stores the address code for the instructions
in ROM 298 which can be resumed at the end of each break.
Memory Control Processor
With the foregoing description of the task priority logic section 200, the
organization of the memory control processor 150 will now be taken up. It
is to be noted that the technique expanding the working memory from three
storage levels is the subject matter of the aforementioned patent
application entitled "Memory Control Processor," filed of even date, and
any detailed considerations of the processor 150 will necessarily entail
consideration of this referenced application. Accordingly, the following
description will deal with the structure shown in FIG. 3 which presents
the memory control processor 150 only to such an extent as is necessary to
complete the description of the present system, reference to be made to
said aforementioned application Ser. No. 769,611 for the details thereof.
As shown in FIG. 3, the memory control processor 150 comprises a random
access accelerator store section, referred to herein as the page buffer
store, system 900 a controller stage 800 and an overlay system implemented
herein according to a Least Recently Used access algorithm and therefore
denominated as an LRU system 1000. The choice of the LRU algorithm is a
specific implementation, but overlays are controllable by any logical
algorithm. Within the controller stage 800 a scratch pad RAM 801 is
provided having a plurality of fields some of which operate to store the
next instruction address in the priority unit 200 (i.e., the address of
the code emanating from the instruction register 299) while some others
being assigned and shared for external service such as service of the
floppy disc system 18.sub.1 - 18.sub.3. The address input to RAM 801 is
obtained from a multiplexer 802 tied to select either the contents of bus
A or the output of register 299. Thus the address to the scratch pad
memory 801 is either direct from the text processor 50, for example, or as
a function of the task execution cycle. The data input to memory 801 is
through a local bus W which originates at a multiplexer 803 collecting and
selecting between the outputs of the overlay or RLU logic 1000, an
arithmetic logic unit (ALU) 804, and a B-register 805. Register 805, in
turn, stores the output of a multiplexer 806, bus D or bus A where
multiplexer 806 receives the A, D and W buses while the ALU 804 completes
the loop by collecting the output of memory 801 and the B-register 805.
The controller 800 outputs from memory 801 into bus D (across appropriate
bus drivers) and across an A-register 809 from multiplexer 803.
The foregoing arrangement provides for a broad and flexible system which
can be selectively configured to any desired mode by the control inputs to
the various multiplexers and the ALU.
Buses A and D, furthermore, input to a C-register 310 in the page buffer
system 900, register 310 being once again controlled by the code appearing
on the PB control outputs of the instruction register 299. To respond only
to certain PB codes the control input to register 310 is produced by a
controller 311, decoding the PB code and thus configured as a decoder or
filter of particular bit combinations. The C-register 310 then provides
the appropriate address input to a random access accelerator store or page
buffer store 301 which is coupled in the data read and write connections
to a data outregister 320 and a data register 330, both of which are tied
to bus D.
It is therefore the function of the page buffer store 301 to provide an
accelerator function to the external bus system. To achieve this function
various lower level memory contents are promoted and demoted in and out of
the page buffer store according to acceptable overlay algorithms in the
overlay system 1000. The implementation of one such overlay scheme is
carried out more extensively in said aforementioned application Ser. No.
769,611 reference should be made thereto for further details.
DISPLAY PROCESSOR
The present system includes a display processor 100 driving a CRT display
101. While in many data processing applications the immediate display of
data is not generally necessary, most interactive uses dictate some visual
communication with the operator. In word processing, in particular, the
ability to provide a soft display of the text which is then edited or
otherwise manipulated by the user is critical if one is to avoid
repetitive production of hard copy as each document is organized. Although
particularly suited for such word processing, the integration of a video
display, however, is advantageous in other uses and the present system
includes the provisions for such a display.
Processing of characters alone, however, is often insufficient in view of
the other potential uses of the system. Accordingly, in addition to a
character generation feature, the display processor includes a facsimile
section thus being capable both of text and graphical display.
A generalized layout of a display processor useful herein is shown in FIG.
4, it being understood that such is illustrated for completeness only.
While there are various implementation techniques in the interest of
generality only gross functions are shown. As shown in FIG. 4, the display
processor 100 communicates with buses A and D across an interface state
102. Interface 102, loads, in coded form, both the text characters and the
various display control instructions into a list memory 103 which
accumulates a serial list of characters and operations necessary to fill
out the screen of the CRT 101. For this purpose, the list memory is
approximately 8 K bytes large, such capacity being necessary to accomodate
a typical 81/2 .times. 11 inch document. Tied to the list memory 103 is a
character generator 104 and an associated font memory 105, the latter
providing the dot matrices for the various characters displayed. Thus the
text characters are fed to the display processor 100 in coded form, such
as the ASCII code which is converted to dot format by the font memory 105.
These dot arrays are then returned to the character generator 104 to be
serially brought out into a line buffer 106 connected to control a video
output register 107. Associated with the horizontal line buffer 106 is a
horizontal counter 108 providing the horizontal deflection signal to the
CRT 101. The vertical deflection signal, in turn, is originated at the
character generator 104 during the line-by-line raster separation of data
for the line buffer 106.
In a similar manner, facsimile data is impressed on to buses A and D in
compressed code format which is expanded by a facsimile memory 111 and
applied to a facsimile generator 112. Generator 102 then provides a
parallel signal to the output register 107, in synchronism with the
vertical and horizontal deflection signals. Thus all of the video
processing, including display refresh, deflections, blanking and other
functions operates totally independent from the system busses. The only
data exchange is by way of inputs to the list memory 103 and fax memory
111 which can occur at any rate used by the overall system.
Also shown by way of a dashed signal lead is a direct path between
interface 102 and the font memory 105. This provides for a loading path
for the dot patterns forming characters in a font. Alternatively ROM's may
be used as memory 105, further simplifying system architecture. It is to
be noted that the display processor 100 further reduces the processing
load in the system by automatically calculating character displacement,
once more, according to data in memory 105.
Again, it is necessary to note that the foregoing description of the
display processor 100 is on the general level only. The operative features
of the present invention can function without the assistance of a display
processor, by way of the printer provided.
BUS SYSTEM
With the foregoing descriptions of the various processing elements which
are tied to a common bus, the implementation of the bus system and the
various controls associated therewith will now be taken up. As shown in
FIG. 5, bus A comprises 17 lines of address, labeled as lines A.sub.0 -
A.sub.16. Bus D includes 16 lines, again labeled as lines D.sub.0 -
D.sub.15. In the above description of the present system 10, the various
devices are shown tied to the bus system across separate interface devices
(e.g. interfaces 13 and 15, and controls 17, 19, and 21). This
implementation, while functionally correct, would entail redundancy in the
bus architecture, and therefore in physical arrangement contains many
instances of shared logic.
Thus, the bus system is shown to include a common interface section 400 to
which the various interfacing devices are tied. The interface section 400
selects the particular device addressed, identifies the operation (order)
which is to be performed in combination with the selected device, and
otherwise organizes bus performance. Thus the A bus, for example, is shown
tied by bit leads A.sub.11 - A.sub.13 to a 3-line-to-8-line decoder 401,
such as the decoder built by Texas Instruments, under the model No.
SN74155. Decoder 401 then provides 8 discrete lines each identifying a
particular device. Bus leads A.sub.14 - A.sub.16 are tied to a similar
decoder 402 which identifies the operation to be performed by the device
selected. In order to separate this direct input-output operation from the
task associated operations, the S bus includes a gating lead EN tied to
the chip enable terminals of decoders 401 and 402 which, when high,
distinguishes this operation from indirect operations involving the MCP
150.
When enabled decoder 401 selects a particular device by setting one of the
eight outputs high; concurrently, the encoder 402 selects the operation.
Since there are many instances where similar operations are performed by
the various devices selected, a common preassigned code is utilized
throughout. Thus, by reference code appearing on the input leads tied to
encoder 402, i.e., leads A.sub.14 - A.sub.16 the following order table is
provided:
______________________________________
A.sub.14
A.sub.15
A.sub.16
______________________________________
1 1 0 = device addressed by
encoder 401 to load
D bus contents onto its
data receiving register
1 1 1 = device addressed by
encoder 401 to load its
command register with
contents of D bus
0 0 0 = Reset device
1 1 0 = selected device to load
(output) its data register
onto D bus
1 1 1 = selected device to load
status code onto D bus
______________________________________
From the above list, it is apparent that at least the 110 and 111 order
codes appear in two directions. Thus, an additional control lead RW is
included in bus S to control the direction. This signal is tied directly
to an AND gate 411 and across an inverter 415 to an AND gate 412. Gates
411 and 412, therefore, control the direction of data transfer between the
selected device and bus D. These control signals, identified as signals
D-in and D-out, are in turn collected in the selected interface circuit at
corresponding AND gates 421 and 422 with the device selecting lead from
decoder 401. Gates 421 and 422, in turn, each enable a corresponding
in-register 431 and out-register 432 which are connected in parallel to
the bit leads D.sub.0 - D.sub.15 in bus D.
It is necessary to note that gates 421 and 422, and the corresponding
registers they control are repeated in each interfacing device. Thus, the
D-in and D-out signal will be fanned out to as many interfacing devices as
are included in system 10. Each interfacing device, however, besides these
common elements will include the specific structure dictated by the
peripheral device. Accordingly, by way of example, the architecture of
controller 21 is shown connected therewith, it being understood that all
the other interfaces are similarly connected. Again, by reference to FIG.
5, registers 431 and 432 also comprise the front section of controller 21.
The output of register 431 is parallel loaded into a shift register 441
which in the data load or in mode is shifted by the gear clock (sector)
signal GC of the main memory disc 20. During this time, the data word
loaded from bus D is serially shifted onto the disc on lead R. In the out
mode data is serially loaded from disc 20 onto the same register 441,
again by the disc gear clock, and is output into register 432.
As has been previously stated, the selection of registers 431 or 432 is
under the control of decoder 402 and the state of signal RW. Since the
operations involved are the device data in and out operations
corresponding to a 110 code at the input to decoder 402, this operational
mode is selected by the second highest lead thereof which is concurrently
applied to gates 411 and 412.
Two additional operations occur in this exemplary interface. For example,
when decoder 402 identifies a command operation directing disc 20 to
perform certain operations the output of this decoder corresponding to an
input code 111 is applied to two AND gates 413 and 414 which also
respectively collect signal RW, gate 414 receiving this signal across an
inverter 417. The outputs of gates 413 and 414 are, in turn, collected
with the device selection decoder 401 output in yet another pair of AND
gates 423 and 424, gate 423 enabling a command register 433 and gate 424
enabling a status register 434. The registers receive and transmit the
respective status and command codes of the disc 20.
In addition to the above connections, the discrimination between a direct
peripheral access and an access entailing task servicing is also
accommodated by the circuit 400. More | | |
