A slowly varying bias signal is added to one input of a Wave Form Transition Sequence Detector, as more fully described in a related application cited herein, to provide a differential output therefrom which is directly proportional to the time between transitions occurring on two input wave forms. The slowly varying bias modulates the level of one input wave form, and thereby varies the time required for the Wave Form Transition Detector to detect a transition occuring thereon. By symmetrically varying the response time of the Wave Form Transition Sequence Detector to one input wave form in the neighborhood of the occurrence of a transition on the second input waveform, the average differential output of the Wave Form Transition Sequence Detector over a cycle of the slowly varying bias level will be proportional to the time between transitions occurring on the two input wave forms.

A flip-flop having a sleep mode in which power consumption is reduced. The flip-flop comprises a clock input, a data input, an input stage, an input gate, an output stage and an output clamp. The input gate is interposed between the data input and the input stage and operates in the sleep mode to isolate the input stage from the data input. The output stage is coupled to the input stage and includes an output having a first output state and a second output state. The output clamp operates in the sleep mode to set the output stage to a predetermined state regardless of the data states at the data input and the clock input. The predetermined state is the one of the output states in which the leakage power consumption of the flip-flop is less than in the other of the output states. The predetermined state may alternatively be the one of the output states in which the leakage power consumption of circuitry connected to the output of the flip-flop is less than in the other of the output states. As a further alternative, the predetermined state may be the one of the output states in which the leakage power consumption of a digital electronic circuit of which the flip-flop forms part is less than in the other of the output states.

A latching circuit comprises: a logic gate circuit having N inputs, such as NAND or NOR; N first switches responsive to a control signal indicative of a latching and non-latching modes for connecting N input terminals to said N inputs respectively in said non-latching mode; a signal producing circuit for producing a signal at an output thereof in response to said logic output; a second switches for connecting said output to said one input in said latching mode; (N-1) third switches responsive to said control signal for connecting N-1 inputs of said N inputs other than said one input to a logic level respectively in said latching mode, said logic level being determined such that said logic outputs is determined by a logic level of said one input in said latching mode, said signal producing circuit producing said signal such that said logic gate circuit holds said logic output in said latching mode. An AND gate and OR gate can be used also. The second and third switches can be replaced with resistive elements. All inputs of the logic circuit may be fed back to latch the output level.

Two switching elements are cross-coupled in the standard bistable multivibrator arrangement. Two additional switching elements are added: one each in parallel with one of the switching elements forming the bistable multivibrator. The two wave forms under study are applied to the control gate of each of the additional switching elements. When both wave forms are in one state, the two additional switching elements are switched ON, effectively inhibiting bistable multivibrator action. The first wave form to change state results in its associated switching element switching OFF, which releases the bistable multivibrator circuit to assume the corresponding stable state, which observed differentially across the switching element forming the bistable multivibrator, is indicative of the wave form to first undergo transition. After the first wave form has undergone transition, the bistable multivibrator becomes insensitive to the subsequently occuring transition on the second wave form, and the circuit remains in the defined stable state until both wave forms again assume their previous state prior to transition, in which, once again, bistable multivibrator action is inhibited.

A first transistor is connected to a second transistor so that the first and second transistors may be initially biased in a non-conducting state when a first node is at a first voltage potential and a second node is at a second voltage potential. A potential altering circuit selectively alters the voltage potential at the first and second nodes, causes the first and second transistors to be in a conducting state for accelerating a voltage transistion at the first and second nodes toward final values, and maintains the first and second nodes at their final voltage potentials for implementing a desired Boolean function. The biasing circuit is connected to facilitate turning off the first and second transistors when the circuit is being reset for subsequent Boolean evaluations. More specifically, the biasing circuit inhibits current flow through the first and second transistors during a precharge operation to prevent excessive power consumption. The circuit according to the present invention may be employed in a number of logic applications such as simple OR/NOR or AND/NAND circuits, generalized parallel/serial logic networks, comparators, etc.. When employed in a chain, such as in a generalized parallel/serial logic network, NMOS circuit elements may be employed together with gate coupling circuitry to ensure high speed operation with minimum size.