This disclosure relates to an electrically alterable amorphous memory device which can be switched from a high resistance state to a low resistance crystalline state. The device has increases in the concentration of those particular elements at the electrodes to which the respective constituents would migrate during a large number of set-reset cycles. This lessens the decline in the threshold voltage caused by the electromigration of those constituents. There is disclosed a layered structure in which a layer rich in one appropriate constituent is placed between the amorphous memory material layer and the respective electrode and another layer of material rich in the other constituent is placed between the amorphous material and the other electrode. Specifically, there is disclosed a tellurium based chalcogenide as the memory layer. A layer of substantially tellurium is placed between the amorphous memory layer and the positive electrode while the layer of germanium and tellurium in a ratio of approximately 1:1 is placed between the amorphous material and the negative electrode.
The first fire voltage of amorphous memory devices are reduced by forming the storage element of two layers, the first being in the crystalline state and the second being the amorphous state. The process deposits a first layer of switchable material and raises the temperature to crystallize the first layer. The wafer is then cooled and the remainder of the switchable material to form the storage element is deposited in an amorphous state.
A phase-change memory may be formed with at least two phase-change material layers separated by a barrier layer. The use of more than one phase-change layer enables a reduction in the programming volume while still providing adequate thermal insulation.
A chalcogenide memory cell with chalcogenide electrodes positioned on both sides of the active chalcogenide region of the memory cell. The chalcogenide memory cell includes upper and lower chalcogenide electrodes with a dielectric layer positioned therebetween. The dielectric layer includes an opening defining a pore. A volume of chalcogenide material formed integral to the upper chalcogenide electrode is contained within the pore. The upper and lower chalcogenide electrodes both have greater cross sectional areas than the pore.
A residual crystallization retardation layer is provided between the non-crystalline switchable semiconductor layer and each electrode structure. Amorphous germanium, silicon or carbon form good crystallization retardation layers and also minimize electromigration and reduce solubility of tellurium in the electrodes.
A phase change layer may switch between more and less conductive states in response to electrical stimulation. The phase change layer may be positioned over a non-switching ovonic material which acts as an electrode, a resistive heater, and an insulating barrier. The phase change layer may be positioned over a non-switching ovonic material which acts as an electrode, a resistive heater, and a thermal barrier.
