A register control instruction is added in a stored program computer and uses the same OP code as used for an existing storage instruction. A non used bit state in the existing storage instruction identifies the instruction as a register control instruction rather than a storage instruction and causes logic to generate a control signal for inhibiting the storage operation whereby the storage address is used for addressing a register instead of storage and data is transferred to or from the addressed register as per other control information in the instruction. The bit state identifying the instruction as a register control instruction is converted to a used bit state of the storage instruction so as to invoke an address update operation normally invokable by the storage instruction to update the storage address used instead for register addressing.
Extended control word decode circuitry increases the number of simultaneous functions performed during execution of a control word in the central processing unit (CPU) of a computer system. A first field of a control word is decoded into 2.sup.n decodes for testing or specifying a first set of CPU conditions. A second field in the control word is decoded into 2.sup.m -X decodes for testing or specifying a second set of CPU conditions. The X decodes, which together with the 2.sup.n decodes of the first field test or specify multiples or pairs of a third set of CPU conditions and inhibit the 2.sup.n decodes from testing or specifying said first set of CPU conditions.
A data processor includes a base register for a base address modification and a program counter for a relative address modification. An instruction executed in the data processor includes an operation code, a first operand, an address modification judgement bit, an index address modification field, a base address modification field and a displacement. When the instruction is fetched, it is arranged in an address modification and a base modification according to the address modification judgement bit. In the case of the relative address modification, the contents of the program counter is added to the contents of the displacement. In the case of the base address modification, the contents of the base register specified by the base address modification field is added to the contents of the displacement. In the relative address modification and the base address modification, the contents of the general register specified by the index address modification is added to the results of the addition, thereby to form an effective address.
A computer includes a memory, a statement translating circuit, and a program executing device. The memory stores a first program with a first command. The statement translating circuit is provided for translating the first command into a second command in a second program. The memory stores the second program with the second command. the program executing device is responsive to the memory for performing the second program with the second command.
A microprocessor, having a memory element containing a plurality of multi-bit instruction words, an arithmetic logic (ALU) unit coupled to the memory element and responsive to at least a portion of each of the instruction words for performing data manipulations, and a controller for generating address signals that are communicated to the memory element to cause sequential access of the instruction words, includes a storage element that interconnects certain of the signal lines that communicate the instruction words to the ALU to the controller. In response to a first predetermined instruction word the storage element receives and stores the portion of the instruction word being conducted to the ALU. In response to a second predetermined instruction word, the content of the storage element is transferred to the controller to form an address signal.
A computer program product, method and apparatus for utilizing common prefix codes in computing instructions so as to reduce the number instructions required to perform identical operations for varying operand sizes. In one form, the common prefix code is appended as the higher order portion of the instruction word to form a second series of instructions. These computing instructions may be utilized in conjunction with a flag register, which, in one application, designates which series of instructions to use; either the original instructions or the modified instructions containing the common prefix. In another application, the flag register designates which register or memory should be used to store the operands and the associated results. Through the use of common prefix codes and the flag register, operands of various sizes can be efficiently manipulated through a simplified scheme of instructions.
