The recovery of a signal on a common bus in a data processing system in which contiguous bus cycles may be generated for the transfer of information between any units coupled to such bus by a method and apparatus which enables such recovery to take place during a first or just completed bus cycle. The following bus cycle takes advantage of an arrangement by which the signal may not be stable until a predetermined point in time in each bus cycle. Data, address and control signals may be recovered by this method and apparatus which uses termination resistors on the bus which are greater in value than the characteristic impedance thereof.
A data processing unit's request to a data processing device for the transfer of control and processing of an operation in response to an instruction from the unit, is stalled by the device, dependent on the type of instruction, for a period of time, also dependent on the type of instruction, until the device is ready to process such operation. A shift register arrangement is used in the device, which, dependent on the indicia stored therein, which indicia are appropriately loaded in such register dependent on the type of instruction, is used to delay a response to the unit by requesting the unit to make another request to the device to process the operation called for by the instruction.
A method and apparatus for use in transmitting information on a wired-OR signal line is described which employs a data transfer protocol exploiting the generally shorter signal settling time occurring following high to low signal voltage transitions than occurs following low to high signal voltage transitions. In accordance with the protocol, the transmission of meaningful information on multiple-driver signal lines is restricted to the assertion of high to low signal voltage transitions. By asserting meaningful information only on high to low transitions, the clock period for the bus may be set based on the voltage settling time resulting from only high to low transitions rather than from arbitrary transitions. As a result, the transmission of meaningful signals are all within the limits of incident wave switching and a high overall information transmission rate is achieved. The amount of information transferable per clock cycle depends upon whether the wired-OR signal line is a single driver line, a multiple driver line wherein events are correlated with commonly observable events, or a multiple driver line wherein events are not correlated with commonly observable events. For single driver lines, one unit of information per clock cycle may be transmitted. For multiple driver lines which are correlated with commonly observable events, one unit of information may be transmitted every two clock cycles. For multiple driver lines which are not correlated with commonly observable events, one unit of information per three clock cycles may be transmitted. Method and apparatus embodiments of the invention are described in particular with reference to a multiprocessor computer system having a latched wired-OR bus.
A bus arbitration arrangement for resolving competing requests for access to a bus is associated with local signal control lines, that are coupled to its associated "master" (i.e. user of the bus), and control lines of the bus common to all other units. These local signal control lines include a set of identification lines defining the address (and priority rank) of the associated master, a request line through which the master requests access to the bus, a grant line through which a master is informed that it has control of the bus, and a release line through which the master informs the bus exchange control circuit that it is releasing its control of the bus. Control lines which are common to other units on the bus include a busy line, through which each interface circuit is advised that the bus is currently in use, a bus clock line for synchronizing the operation of the bus exchange control circuits, a set of bus request lines over which the addresses of users requesting control of the bus are conveyed and through which priority among conflicting requests is resolved, and a select acknowledgement line which is used to terminate priority resolution once it has been determined which requesting user has highest priority. The bus exchange control circuit itself contains a set of combinational logic, which carries out a set of housekeeping chores using the control signal lines, so as to enable its associated master to gain control of the bus when requested and, in the event of a plurality of simultaneous requests, resolving those requests in favor of the master whose identification lines indicate the highest priority among potential users of the bus.
A new polling apparatus for units on a shared bus of a data processing system operates with a relatively slow multi signal line request bus and a relatively slow local counter. The local counter divides each time slot into a few sub-slots. Each sub-slot is assigned to two or more units in a priority sequence and during a sub-slot the assigned units contend for access to the bus by raising signals on particular lines of the request bus according to their priority within the sub-slot.
In a data processing system having a system bus for coupling I/O units to a system storage unit, there is provided a mechanism for supplying to the I/O units a line size signal representing the line size of the system storage unit. A further mechanism is located in at least one of the I/O units for responding to this line size signal for adjusting the data transfer size of the I/O unit to match the system storage unit line size.
