An AC switching device includes a switch element associated with the primary side of a transformer so that the switching element is turned on or off always at a zero-crossing point where the alternating current shifts from predetermined one of the positive and negative phases to the other. The switching element is turned off at a zero-crossing point which occurs immediately after the arrival of a turn-off command signal while it is turned on at a zero-crossing point which occurs after the arrival of a turn-on command and at the same phase of the alternating current as the turn-off phase.

A trickle power supply for a light switch module according to the invention enables power to an electronic circuit to be taken directly off the hot line. The power supply operates under what is referred to as the "switched leg theory". All power is taken off the standard switched leg of the light circuit. The power supply bleeds enough current to power its electronic circuitry without turning on the load device, i.e., the light. At the same time, the maximum current to the load is limited to prevent shorting out of the power supply which would effectively disable the switch module.

A trickle power supply for a light switch module according to the invention enables power to an electronic circuit to be taken directly off the hot line. The power supply operates under what is referred to as the "switched leg theory". All power is taken off the standard switched leg of the light circuit. The power supply bleeds enough current to power its electronic circuitry without turning on the load device, i.e., the light. At the same time, the maximum current to the load is limited to prevent shorting out of the power supply which would effectively disable the switch module.

The present invention impresses the data on the power signal by utilizing a saturable core reactor. The saturable core reactor uses two cores. Each core has both load windings and control windings. The control windings are selectively energized to alter an electrical characteristic of the current passing through the load windings. The saturable core reactor is designed with cores made of a highly magnetically permeable material so that the cores are easily saturated. The cyclical saturation of the cores achieved by the load current, and the selective saturation of the cores achieved by selectively applying a control current, results in "deformations" being selectively formed at the zero crossings of the load current waveform. These "deformations" can be selectively formed on the power signal to represent a binary data stream. Once the series of "deformations" is impressed onto the power signal, the "deformations" are communicated from one point on the power cable to another point on the power cable together with the power signal. The "deformations" are then read and transformed into a binary data stream. Thus, the power cable is converted from a mere power cable to a power cable capable of transmitting both power and data simultaneously.

An industrial automation system using transformers for providing electrical isolation between a system interface chip and a load interface chip while simultaneously allowing communication of power and data across the isolation barrier. Clock pulses are transmitted from the system interface chip to the load interface chip across one transformer, and the clock pulses are used by the load interface chip to create a power supply for operating the components within the chip. Data is communicated from the system interface chip to the load interface chip across a second transformer by the use of messages. Each message comprises a bit sync field, a byte sync field, and a data field. The bit sync field and byte sync field are used by the load interface chip to synchronize itself with the system interface chip. Transmission and reception of data by the chips are interleaved on a bit-by-bit basis, wherein a bit is transmitted from the load interface chip to the system interface chip after each bit is transmitted from the system interface chip to the load interface chip. After each byte of data is transmitted and received by the chips, the load interface chip eliminates synchronization between the chips, and must resynchronize itself with the system interface chip in order to transmit and receive the next byte of data.