A television receiver is provided comprising a variable frequency local oscillator and frequency synthesizer control means for controlling the frequency of the variable frequency local oscillator in accordance with the setting of variable divider means for effecting channel or frequency tuning of said receiver, the frequency synthesis control means comprising first divider means operable on the output of the variable frequency local oscillator, the first divider means being set to one of a plurality of division ratios under the control of fine tuning means associated therewith, variable divider means operable on the output of the first divider means, and phase/frequency comparator means for comparing the output of the variable divider means with a reference frequency and for affording a control signal to the variable frequency local oscillator for controlling its frequency.
A system for the automatic measurement of the level, flow rate, and flow volume of liquid flowing through a channel is described. An echolocation system operates to detect returns from the surface of the liquid in the channel during successive transmission cycles in response to the reflection of sonic signals. A source of pulses having a frequency which provides a certain number of pulses corresponding to the travel time of the sonic signals over a distance equal to a maximum predetermined level or head of the liquid in the channel provides pulses from which the liquid level, flow rate, and flow volume can be obtained. The control of the frequency of the pulses from which the measurements are obtained may be accomplished by a digital phase locked loop system to minimize the effects of changes in ambient condition, such as temperature, vapor pressure, and composition of atmosphere as often occurs in such conduits. The system may therefore be used for monitoring liquid levels in a container, effluents, such as waste water in a sewage system and controlling the sampling of such waste water each time a preset volume thereof is discharged via the conduit. Also solids levels in a container may be measured as may any distance from the transducer according to its preset range.
A frequency prepositioning device for an indirect frequency synthesizer having switchable loops comprises an oscillator controlled by a voltage V.sub.N and at least one programmable prepositioning voltage generator. The device essentially comprises a memory device for storing the values of the prepositioning voltage at each transition to each frequency, thus making the device self-adaptive and capable of self-testing.
A phase-locked loop frequency synthesizer with fine tuning comprises a controlled oscillator, a divider for dividing signals provided by the oscillator, a comparator for comparing signals derived from the divider with a reference signal and for providing a control signal for the controlled oscillator, a fine tuning circuit for providing a fine tuning control signal, and a pulse generator responsive to the fine tuning control signals for providing one or more control pulses to control the divider. The divider preferably comprises a two modulus divider for dividing by one of two factors for a period dependent upon the number of control pulses provided by the pulse generator, and for dividing by the other of the two factors for the remainder of the time period. The pulse generator preferably comprises a pulse detection and synchronization circuit and a control pulse generator, each connected to the output of the two modulus divider.
A circuit arrangement for selecting the tuning of a radioelectric signal in a signal receiving set, in particular a television set, comprises a memory circuit having a plurality of cells for storing in digital form information relating to a plurality of tunable signals with means in the circuit arrangement for sequentially scanning the cells of the memory circuit and for obtaining the stored information for the desired selection of a receiving signal.
A three modulus prescaler for a phase-locked loop frequency synthesizer includes a N.sub.0 modulus prescaler inputting into a divide-by-two circuit. A microprocessor and internal logic control a three modulus prescaler synchronizer to receive signals from the divide-by-two circuit and output control commands to the N.sub.0 modulus prescaler so as to cause the N.sub.0 modulus prescaler to divide solely by a first or second modulus, or alternately between said first and second modulus, between output pulses of the divide-by-two circuit to extend the synthesizer's bandwidth.