A data buffer system is provided for controlling the transfer of data between a processor and an input/output (I/O) device and includes a data storage device having a maximum data storage capacity value. The data storage device is disposed between the processor and the I/O device for receiving data input from the processor and for outputting data to the I/O device to thereby transfer data from the processor to the I/O device. The data storage device temporarily stores a predetermined amount of data while simultaneously transferring data between the processor and the I/O device. Circuitry is provided for selectively establishing a threshold storage capacity value of the data storage device wherein the threshold storage capacity value is less than the maximum storage capacity value of the data storage device. Circuitry is further provided for maintaining the predetermined amount of data temporarily stored in the data storage device equal to the threshold storage capacity value while the data storage device receives data from the processor and outputs data to the I/O device.

Apparatus for producing a circular-queue structure which permits interfacing between a high speed mini-computer and a relatively slow speed microprocessor via a common memory and with multi-device, asynchronous handling capability. The structure also permits commands and data to be chained in the same queue. The apparatus permits multiple devices to be handled simultaneously. By monitoring the memory address which is being accessed by the minicomputer, the information retrieved from the memory by the microprocessor is selectively validated or invalidated.

Apparatus (100) and a method (5) are used for polling asynchronous sensors (1, 2, 3) of a computer system to optimize the data load offered by the sensors to a central processor (4). The polling apparatus and method operate in accordance with time delay status (4200, 4210, 4220) recorded in the sensor buffer stores (420, 421, 422) of the memory unit (42) of the central processor. The system determines the amount of data received in a sensor buffer store during the polling sequence and dynamically varies the value of the time delay status to optimize the load of sensor data offered the central processor.

A plurality of data bands operable independently from each other is controlled by a control circuit so that a set of received data signals are written into respective storage locations predetermined for respective data signals within respective data banks predetermined for respective data signals, wherein respective storage locations and respective data banks for respective received data signals are predetermined depending upon the arrival numbers of respective received data signals and a predetermined bank order, so that respective storage locations for two data signals received one after another belong to different data banks arranged according to the bank order. The data banks are controlled by the control circuit so that a set of data signals are read out according to the order of receipt of the set of data signals and from a timing before completion of the writing of the set under a condition that each data bank performs only one of write and read operations during a clock period.

A data communications system to provide for the dynamic modification of a queue of documents arranged sequentially for transmission. An operator interacts with the send queue by making the send queue selection from a menu of communication request tasks on a display. Selection of the addition to the send queue option invokes a routine to add a send job. Operator selection of the display send queue option invokes a routine to display the send queue in the display for review of the current send queue and its status. A delete send job option invokes a routine to allow the operator to delete any job from the send queue except the one currently being sent. The select next send job option invokes a routine to allow the operator to start or restart the sending process from any point within the send queue.