The phase control arrangement of a valve converter according to the invention comprises a control signal former having one input connected to the valve converter and another input connected to a reference signal unit. The output pulse from the control signal former is fed, concurrently with the output signal of a sawtooth oscillator, to a zero element having its output connected, via a phase limiter, to the input of the control pulse generator. Control pulses are distributed among the converter valves by means of a pulse distributor. The sawtooth oscillator has two inputs of which one is connected to the input of the pulse distributor and the other is connected to the output of the control signal former. The arrangement provides for correspondence of performance parameters of the converter to the preset values and maximum response speed in transient conditions.
A method of digital control of m-phase thyristor-pulse converters, in which the duration of the conductive state of the thyristors of each phase of an m-phase thyristor-pulse converter is changed by sending time-shifted and time-constant pulse trains successively from each control channel to the thyristors of respective phases with simultaneous shift of the onset of operation of the thyristors of each phase by (1/m) period of switching the thyristors. Successive connection of each control channel to a respective phase is effected upon achieving the maximum value of the control zone of each control channel. The apparatus for carrying out the proposed method includes a master oscillator connected to a clock counter whose outputs are connected to the inputs of a decoder for decoding the time-constant pulse trains and to the logic inputs of "m" decoders for decoding the time-shifted pulse trains. The data inputs of each of the "m" decoders are connected to the data outputs of a bidirectional counter connected to a control unit, while the ouput of each of the "m" decoders is connected to one of the "m" data inputs of a matching unit whose control inputs are connected to the control outputs of the bidirectional counter. The matching unit includes "m" groups of AND gates, each group comprising "m" AND gates; the output of each AND gate of the 1-th group is connected to the 1-th control output of the bidirectional counter, while the other input of the 1-th AND gate of each group is connected to the output of the decoder for decoding the 1-th time-shifted pulse train, where 1=1,2, . . . m and m is the number of phases of the polyphase thyristor-pulse d-c converter.
An apparatus for preventing malfunctions in a phase control mechanism of the type in which the firing angle of thyristors in a thyristor bridge is controlled to regulate the rotational speed of a DC motor comprising the load of the thyristor bridge. Thyristor firing pulses are produced each time a rising analog speed command signal generated in response to the phases of a N-phase power supply intersects N-number of sawtooth signals. Immediately after the generation of each firing pulse, the thyristors are not supplied with firing pulses for a time interval at least equivalent to the thyristor commutation overlap time.
